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Article #36Re: 4 layer PCB (from 2 layer) + array of designs on one board
From: vasile
Date: Thu, 28 Dec 2006 08:57
Date: Thu, 28 Dec 2006 08:57
67 lines
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4702 bytes
PCB stack is an invention to minimise the EMI radiation and improve the speed of signals talking in terms of microwave or high frequency propagation. Jumping from 2 to 4 layers will not gave you many improvements in EMI as long the major signals are still routed on top and bottom. The first stack with some performance is a 4 layer stack (counted from top to bottom)as PWR-signal-signal-GND and 6 layer stack (top-signal-PWR-GND-signal-GND-bottom or other similar versions) where top and bottom are mixed signal/ground planes Will be no noise improvement if +5 and -5V routes becomes planes, could be worse. In analogic and RF design the supply lines are usually routed radially from the source (supply) to destination. This not means a contiguous supply plane could be worst as long is in the neigborhood af quiet ground planes. best regards, Vasile Surducan senior application engineer National Institute R&D for Isotopic and Molecular Technologies Cluj-Napoca Romania Vitaliy wrote: > Hello, > > My appplication is light detection -> using photodiodes and > transimpedeance amplifier (OPA657 from Texas Instruments). At this > point I have 2-layer working design. I need to increase the bandwidth > of the detector (from 10MHz to 40MHz) and try to reduce noise (also > reducing noise is always welcome, of course). I'm thinking about using > two inner layers for +5V and -5V power layers (I'm using free space on > top and bottom layers for ground layer). +-5V is currently connected to > the board from external power supply by soldering two wires (one for > +5V and one for -5V). I am using +-5V to bias photodiodes and to power > the opamp. The software I'm using is OrCAD. Even if going to 4 layer > from two wouldn't give me a significant improvement in terms of > reducing the noise level, I would like to know the answers for the > following questions. > > 1) Will traferring +-5V to separate layers (rather than just have the > power traces with filters) work? Since the inner layer is most likely > to be .5oz copper as opposed to 1oz copper of outer layers. There is no > way to specify that in gerber file, right? Will creating a power layer > give me more stable voltage (and high capacitance)? That's why people > are using multilayers as opposed to two layers, right? I guess I will > still need some decoupling capacitors at the vias. > > > 2) The price differential between 2 and 4 layer boards is quite steep, > and I can easily fit a few prototype boards on one board and then cut > them (or have it cut by manufacturer). What is the easiest way to place > array of differemt designs on one board? I only have access to OrCAD, > but it can generate gerber files, so maybe some other software can be > used. Are the manufacturers ok with this? I would prefer them to cut > the boards, if possible, since I probably wouldn't be able to do it as > well without special equipment. (Something tells me they woudn't be > willing to make x by x board, and then cut it in y pieces, but just > checking). I do realize I might be able to place three designs side by > side and not require any cutting, but that might not always work for > me. > > Merry Christmas, > Vitaliy
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X-Google-Thread: 111d0a,98c8f92c95d5cd79 X-Google-Thread: 112d1e,98c8f92c95d5cd79 X-Google-Thread: f849b,98c8f92c95d5cd79 X-Google-Thread: 103407,98c8f92c95d5cd79 X-Google-Attributes: gid111d0a,gid112d1e,gidf849b,gid103407,public X-Google-Language: ENGLISH,ASCII-7-bit Path: arc1-ca.pugleaf.net!g2news2.google.com!postnews.google.com!79g2000cws.googlegroups.com!not-for-mail From: "vasile" <piclist9@gmail.com> Newsgroups: sci.electronics.basics,sci.electronics.design,comp.arch.embedded,aus.electronics Subject: Re: 4 layer PCB (from 2 layer) + array of designs on one board Date: 28 Dec 2006 00:57:18 -0800 Organization: http://groups.google.com Lines: 68 Message-ID: <1167296238.071923.46860@79g2000cws.googlegroups.com> References: <1167029740.938190.304470@n51g2000cwc.googlegroups.com> NNTP-Posting-Host: 193.231.25.43 Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" X-Trace: posting.google.com 1167296248 31410 127.0.0.1 (28 Dec 2006 08:57:28 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Thu, 28 Dec 2006 08:57:28 +0000 (UTC) In-Reply-To: <1167029740.938190.304470@n51g2000cwc.googlegroups.com> User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Complaints-To: groups-abuse@google.com Injection-Info: 79g2000cws.googlegroups.com; posting-host=193.231.25.43; posting-account=BwuUHAwAAACRmdRrnoWOjYONkQajeWhP