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Article #2178Re: seeking 2.5V, 100mhz clock source
From: Bill Sloman
Date: Fri, 21 Nov 2003 11:49
Date: Fri, 21 Nov 2003 11:49
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3709 bytes
jwilliams@itee.uq.edu.au (John Williams) wrote in message news:<3a2cf4e1.0311202341.238a2bab@posting.google.com>... > John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote in message > > > <jwilliams@itee.uq.edu.au> wrote: > > > > >I'm looking for a 2.5V, 100MHz clock source, preferably in a surface > > >mount package. Any part or supplier suggestions? > > > > > >2.5V operation is my highest priority. Existence of an Australian > > >supplier would also be helpful! > > > Um, how accurate? > > Well I'm not measuring the speed of light - but +/- 100ppm or so would > be good. > For any future critical time keeping applications I could use an RTC > chip or whatever. > > > Must it be a crystal oscillator? > > Not necessarily - just simple and stable - basically just solder it in > and off I go... > > > Why 2.5 volts? Clocking an FPGA or something? > > Precisely - and the IO bank onto which this clock comes is driving > some 2.5V DDR, so I don't have a lot of room to manoeuvre. > > The FPGA is actually hosting a soft core microprocessor (running our > linux port no less!), so I'm just generating a processor clock with > it. The FPGA has a digital clock synthesiser inside it that I could > use, but I'd prefer not to "waste" one if I don't need to (since the > DDR drive logic needs a couple as well). > > But I should ask... what are my options for simple and stable 2.5V > oscillators and lower frequencies (24Mhz, 66Mhz, ...)?? Farnell stock two 100MHz crystal-controlled oscillators in SMD packages - order codes 316-0282 (from C-MAC) and 329-8504 (from SaRonix). Both are intended to run from 3.3V supplies. IIRR some low voltage FPGA's can tolerate input voltages that go higher than their supplies, so you might not need to divide or diode clamp the outputs. At 100MHz, low-voltage differential signals (LVDS), which can be terminated without dissipating too much heat, are an attractive option, and some FPGAs offer inputs which can be configured to accept such signals. The C-MAC web-site http://www.cmac.com/mt/databook/ lists SMD oscillators offering ECL and PECL outputs, which have the right sort of limited voltage swing, but probably not at the right DC level - you might be able to do something with capacitor or transformer coupling. I'd use a couple of wide-band transistors in SOT-23 packages(BFR92 for NPN, BFT92 for PNP) to do any necessary level and amplitude switching, but I've done it before. ------ Bill Sloman, Nijmegen
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 112d1e,af96ffe7ab3006ab X-Google-Attributes: gid112d1e,public X-Google-Thread: 103407,af96ffe7ab3006ab X-Google-Attributes: gid103407,public X-Google-Thread: 1118be,af96ffe7ab3006ab X-Google-Attributes: gid1118be,public X-Google-ArrivalTime: 2003-11-21 03:49:42 PST Path: arc1-ca.pugleaf.net!archiver1.google.com!postnews1.google.com!not-for-mail From: bill.sloman@ieee.org (Bill Sloman) Newsgroups: sci.electronics.design,sci.electronics.components,aus.electronics Subject: Re: seeking 2.5V, 100mhz clock source Date: 21 Nov 2003 03:49:42 -0800 Organization: http://groups.google.com Lines: 63 Message-ID: <7c584d27.0311210349.12f86a1a@posting.google.com> References: <bphiip$4sm$1@bunyip.cc.uq.edu.au> <9ujorv85nrfu69bnhgbujrp2m87h42587s@4ax.com> <3a2cf4e1.0311202341.238a2bab@posting.google.com> NNTP-Posting-Host: 62.131.10.18 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Trace: posting.google.com 1069415382 22260 127.0.0.1 (21 Nov 2003 11:49:42 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 21 Nov 2003 11:49:42 +0000 (UTC)