🚀 go-pugleaf

On Wed, 30 Oct 2002 07:58:41, "Jeroen" <none@none.nl> wrote:

> "Jim Backus" <JHB@jita.nospam.demon.co.uk> wrote in message
> news:vdCZ2p92dNiH-pn2-i8VcFlNzYkRj@localhost...
> > Any serial comms experts out there able to answer this:
> >
> > I'm thinking about synchronous NRZ data with an accompanying 1 x
> > clock.
> >
> > Similarly looking at the receive data, should the space to mark
> > transition of the clock be spaced half a bit period into each bit?
> 
> Data needs to be stable before you can clock it into a D-flipflop. So it's
> better that the clock comes a bit later than the data, half a bit space
> would be ok.
> 

Thanks - in the cold light of day that's very sensible.

I'm going to post a timing diagram on 
alt.binaries.schematic.electronics showing the timing I'd expect. My 
experience with serial comms has mainly been with asynchronous data on
RS232 lines. The RS422 standard is not clear regarding the polarity of
the A & B lines. When people also use +ve and -ve to indicate the 
polarity, and the two different nomenclatures are used in different 
places in the same system, and there is the possibility of errors on 
the drawings, it all gets very confusing. The system I'm looking at is
normally configured so that both the data transmitter and receiver 
operate with an externally spplied clock. I want to establish what the
timing relationship should be between a synchronous flag byte (HDLC) 
and the clock.

--
Jim Backus  OS/2 - smarter than the average operating system
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