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Article #823

Re: Rigol caught with their pants down! (DS1052E Oscilloscope)

#823
From: langwadt
Date: Tue, 21 Jul 2009 11:42
34 lines
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On 20 Jul., 03:11, krw <k...@att.bizzzzzzzzzzz> wrote:
> On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
>
> <altz...@gmail.com> wrote:
> >a7yvm109gf...@netzero.com wrote:
>
> <snip>
>
> >> You corrected the number of PLLs in the FPGA, how do they get the
> >> clocks' phases aligned?
>
> >Beats me.
> >Could be as simple as fixed tuned gate delay inside the FPGA, or could be
> >some more complex system that auto-calibrates perhaps.
>
> Tuning gate delays in an FPGA doesn't work.  Routing is over half the
> delay and there is no way to fix that part.  Every time you "wire" the
> part it'll have a different routing and your delays will be off.
> Indeed, the idea is to make sure you don't rely on placement or
> routing.
>
> <snip>

I think you can place and wire parts of it by hand to get around some
of it, but it would
still change with temperature, voltage, etc.

Some Xilinx fpgas have programmable delays in the IOs, 64taps each at
1/64th of a ~200MHz (afair)
reference clock.  a closed loop keeps the delay constant with temp
etc.

-Lasse
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From: "langwadt@fonz.dk" <langwadt@fonz.dk>
Newsgroups: sci.electronics.design,aus.electronics
Subject: Re: Rigol caught with their pants down! (DS1052E Oscilloscope)
Date: Tue, 21 Jul 2009 04:42:36 -0700 (PDT)
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