🚀 go-pugleaf

On 22 Jul., 01:14, krw <k...@att.bizzzzzzzzzzz> wrote:
> On Tue, 21 Jul 2009 04:42:36 -0700 (PDT), "langw...@fonz.dk"
>
>
>
> <langw...@fonz.dk> wrote:
> >On 20 Jul., 03:11, krw <k...@att.bizzzzzzzzzzz> wrote:
> >> On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
>
> >> <altz...@gmail.com> wrote:
> >> >a7yvm109gf...@netzero.com wrote:
>
> >> <snip>
>
> >> >> You corrected the number of PLLs in the FPGA, how do they get the
> >> >> clocks' phases aligned?
>
> >> >Beats me.
> >> >Could be as simple as fixed tuned gate delay inside the FPGA, or could be
> >> >some more complex system that auto-calibrates perhaps.
>
> >> Tuning gate delays in an FPGA doesn't work.  Routing is over half the
> >> delay and there is no way to fix that part.  Every time you "wire" the
> >> part it'll have a different routing and your delays will be off.
> >> Indeed, the idea is to make sure you don't rely on placement or
> >> routing.
>
> >> <snip>
>
> >I think you can place and wire parts of it by hand to get around some
> >of it, but it would
> >still change with temperature, voltage, etc.
>
> You might do it once.  You'll never maintain the mess.
>
> >Some Xilinx fpgas have programmable delays in the IOs, 64taps each at
> >1/64th of a ~200MHz (afair)
> >reference clock.  a closed loop keeps the delay constant with temp
> >etc.
>
> Yes, there is an I/O delay, but it's certainly not that large.  There
> is also delay in the DLLs on that order, but there are a lot of
> restrictions on those (clocks only).

had to check, virtex5 has a programmable IOdelay, 64 taps of each
~78ps with the nominal 200MHz reference

-Lasse