Re: Rigol caught with their pants down! (DS1052E Oscilloscope)

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From: a7yvm109gf5d1
Date: Sun, 19 Jul 2009 15:47

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On Jul 19, 7:04 am, "David L. Jones" <altz...@gmail.com> wrote:
> As promised, an exposé of an issue with the Rigol DS1052E oscilloscope in my
> latest video blog:http://www.alternatezone.com/eevblog/
>
> Dave.
> --
> ---------------------------------------------
> Check out my Electronics Engineering Video Blog & Podcast:http://www.alternatezone.com/eevblog/

You corrected the number of PLLs in the FPGA, how do they get the
clocks' phases aligned? I'm no expert on digital scopes, but I suppose
the clock frequency changes depending on the time base?
Do they just drop some ADCs and keep the frequency, thereby permitting
the use of trace delays to get the 100ps delays or what?
Are the GS/s figures real time or equivalent time?
I think it is possible Rigol tests the ADCs and bins them in-house. Do
you think they might run the power supply a bit "hotter" to get the
parts to work at higher clocks?

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Subject: Re: Rigol caught with their pants down! (DS1052E Oscilloscope)
Date: Sun, 19 Jul 2009 08:47:35 -0700 (PDT)
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