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Article #855

Re: Rigol caught with their pants down! (DS1052E Oscilloscope)

#855
From: krw
Date: Mon, 20 Jul 2009 01:11
21 lines
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On Mon, 20 Jul 2009 07:52:09 +1000, "David L. Jones"
<altzone@gmail.com> wrote:

>a7yvm109gf5d1@netzero.com wrote:

<snip>

>> You corrected the number of PLLs in the FPGA, how do they get the
>> clocks' phases aligned?
>
>Beats me.
>Could be as simple as fixed tuned gate delay inside the FPGA, or could be 
>some more complex system that auto-calibrates perhaps.

Tuning gate delays in an FPGA doesn't work.  Routing is over half the
delay and there is no way to fix that part.  Every time you "wire" the
part it'll have a different routing and your delays will be off.
Indeed, the idea is to make sure you don't rely on placement or
routing.

<snip>
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From: krw <krw@att.bizzzzzzzzzzz>
Newsgroups: sci.electronics.design,aus.electronics
Subject: Re: Rigol caught with their pants down! (DS1052E Oscilloscope)
Date: Sun, 19 Jul 2009 20:11:55 -0500
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