🚀 go-pugleaf

 (Wilbert Knol) writes:

> At work I have been given the task to design and build a power amplifier
> with roughly the following specs: output power 5000W av. during 10 ms,
> load 50 ohm resistive, off-time 1.99 s, -3dB bandwidth: 38 kHz +- 5 kHz,
> linear mode, solid state, mains powered (240 V/ 50 Hz).
> [...] 

I can offer a few tips...

Class B is a good choice. The maximum theoretical efficiency is 78%; if you
used PWM, you could squeeze a bit more efficiency at the expense of more
design effort.

Because of the low duty cycle, you can take advantage of the transient thermal
impedance characteristics to reduce the size of your heatsink. I looked at
several curves for International Rectifier HEXFETs and found that for your
duty cycle, you can reduce the junction-case thermal impedance from 20%
to 40% of it's original value.

I've never done a high-power linear amplifier design, but as long as it's
linear, I'm sure you can use small-signal analysis. The only thing I would be
REALLY careful about is oscillation; make sure your loop gain is well below
unity at 180 degree phase shift. 

Since you are using a push-pull center-tapped transformer topology, be aware
that the peak Vds across your output drivers is TWICE the value of the DC
supply voltage. Although an H-bridge takes four devices (instead of 2),
you don't have the Vpeak = 2* Vsupply problem.

Watch out for beats produced by the phase relationship between the AC supply
voltage and the voltage dips on your capacitor bank as the amplifier is
driven. I would suggest phase-locking your 10 msec 'blasts' to the zero-cross 
of the AC line. I'm assuming this is some kind of sonar device, so you will
probably want your 'blasts' to have closely-matched profiles. If you don't
phase-lock, some blasts will occur while the capacitors are charging (and
thus have higher energy); others will be powered solely by the capacitor
bank and thus have lower energy because the capacitors are discharging.


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