🚀 go-pugleaf

heacock@kuhub.cc.ukans.edu (Doug Heacock) writes:
>
>>LED's in sequence, one after the other.  Here's my idea so far:  I
>>intend to use half of a 4011 (quad 2-input NAND gate) as a clock
>>oscillator to drive half of a 4518 (dual synchronous up counter),
>>which will in turn drive a 4028 (BCD-to-decimal decoder), which will
>>actually drive the LED's.  I was thinking I could connect all of the
>>LED cathodes to ground through a single 330-ohm resistor, since only
>>one would be lit at a time.
>
>>Does this sound workable?  I welcome more elegant solutions--these
>>chips just happen to be the ones I have on hand at the moment.
>>+-----------------------------------------------------------------+
>>| Doug Heacock, Academic Computing   | heacock@kuhub.cc.ukans.edu |
>>| Services, The University of Kansas | heacock@ukanvax.bitnet     |
>>| Lawrence, KS 66045                 | Amateur radio: N0NZQ       |
>>+-----------------------------------------------------------------+

For halloween I made a simple light sequencer for my halloween costume
(I was going to a rave, and wanted to blink blink blink).  Anyway, this
is what I did.  

First of all this is the original design:

1 PALCE22V10 (I could have used any other pal with at least 5 outputs,
but I had this one handy)... It was programmed as follows:
	5 state variables
	1 input MODE.

	when MODE was 0, the pal would count from 00000 to 01111 and
then back to 00000 again.

	when MODE was 1, the pal would count from 00000 to 01111 to
11111 to 11110 to 11101 to 11100 to 11011 all the way back down to 10000
and then back to 00000.  So in other words it counted up and then down.
If I hadn't wanted this feature, I would have just used a simple
counter.

1 74LS154 4 to 16 line decoder which was hooked up to the 4 lsb's of the
pal.

1 555 timer with appropriate connections and r and c for an astable
multi-vibrator (read clock signal generator).

2 resistor networks (330 ohms)

48 leds to be hooked up as follows:

+VCC----|>---VVVVVV----- output of 154
       LED    330 ohm    ground when asserted

Since the 154 has negative logic outputs this set worked really well,
when the output was unasserted, it would remain high and stop any
current from flowing through the led circuit, and when it was asserted
it would go low and sink the current from the led circuit.

Well this design would have worked fine and everything, but when I
Implemented it I accidentally bought the wrong resistor networks, and
instead of buying a resistor network with x amount of separate
resistors, I bought a network where a common end of each resistor was
tied together to one pin like so:


 /---VVVVV---
 | /-VVVVV---
-----VVVVV---
 | \-VVVVV---
 \---VVVVV---

This would have worked to but I would have had to run both leads of both
LEDS back to the R-network and since this was double the amount of wire
needed, I decided to go with my actual design where:

I connected the leds directly from the output of the 154 to the led and
the other end to ground.  Of course this created the converse effect
where only one light was off at one time, but it was still neat.  

The actual costume consisted of a control and logic back that I had on
my chest, connected to 4 1.5 Volt AA batteries (Vcc = 6volts), 16 leds
connected in front in an infinity symbol so that when the brain was in
MODE 0, the inifinity would look like it was cycling.  In the back I
used the other 32 leds do realize the following pattern:


         13    14

          9    10      
                     
          5     6      
                     
16 12  8  1  2  3  7  11  15
                     
          4     4
                     
15 11  7  3  2  1  8  12  16 
                     
          6     5      
                     
          10    9
	
	  14   13


Where the different numbers represent the different 154 outputs...

Here is the PAL file I used.   I hope I didn't bore everyone too much...


;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    Rave halloween brain
PATTERN  rave.pds
REVISION 1.0
AUTHOR   Mark Dochtermann
COMPANY  RIT
DATE     10/29/92

CHIP  rave PAL22V10

;---------------------------------- PIN Declarations ---------------
PIN  01         CK                                               ; INPUT 
PIN  02         MODE                                             ; INPUT 
PIN  03         NC                                               ; INPUT 
PIN  04         NC                                               ; INPUT 
PIN  05         NC                                               ; INPUT 
PIN  06         NC                                               ; INPUT 
PIN  07         NC                                               ; INPUT 
PIN  08         NC                                               ; INPUT 
PIN  09         NC                                               ; INPUT 
PIN  10         NC                                               ; INPUT 
PIN  11         NC                                               ; INPUT 
PIN  12         GND                                              ; INPUT 
PIN  13         OE                                               ; INPUT 
PIN  14         NC                                               ; OUTPUT
PIN  15         NC                                               ; OUTPUT
PIN  16         NC                                               ; OUTPUT
PIN  17         Q0                                               ; OUTPUT
PIN  18         Q1                                               ; OUTPUT
PIN  19         Q2                                               ; OUTPUT
PIN  20         Q3                                               ; OUTPUT
PIN  21         Q4                                               ; OUTPUT
PIN  22         NC                                               ; OUTPUT
PIN  23         NC                                               ; OUTPUT
PIN  24         VCC                                              ; OUTPUT

;----------------------------------- Boolean Equation Segment ------
EQUATIONS
Q0 := 	Q1*/Q4*/Q0 +
	/Q1*/Q4*/Q0 +
	MODE*Q1*Q2*Q3*/Q4 +
	MODE*/Q0*Q1*Q4 +
	MODE*/Q0*/Q1*Q2*Q4 +
	MODE*/Q0*/Q1*Q3*Q4
Q1 :=	Q0*/Q1*/Q4 +
	/Q0*Q1*/Q4 +
	Q0*Q1*Q4*MODE +
	Q1*Q2*Q3*/Q4*MODE +
	MODE*/Q0*/Q1*Q2*Q4 +
	MODE*/Q0*/Q1*Q3*Q4
Q2 :=	Q0*Q1*/Q2*/Q4 +
	/Q1*Q2*/Q4 +
	Q0*Q1*Q3*/Q4*MODE+
	/Q0*Q1*Q2*/Q4+
	Q1*Q2*Q4*MODE+
	Q0*Q2*Q4*MODE+
	/Q0*/Q1*/Q2*Q3*Q4*MODE
Q3 :=	/Q2*Q3*/Q4*/MODE+
	/Q1*Q3*/Q4*/MODE+
	Q0*Q1*Q2*/Q3*/Q4+
	/Q0*Q1*Q2*Q3*/Q4*/MODE+
	Q3*MODE*/Q4+
	Q1*Q3*Q4*MODE+
	Q0*Q3*Q4*MODE+
	Q2*Q3*Q4*MODE
Q4 :=	Q3*Q4*MODE+
	Q2*Q4*MODE+
	Q1*Q4*MODE+
	Q0*/Q1*/Q2*/Q3*Q4*MODE+
	Q0*Q1*Q2*Q3*/Q4*MODE
	
;----------------------------------- Simulation Segment ------------
SIMULATION
TRACE_ON CK CK Q0 Q1 Q2 Q3 Q4 MODE                   
SETF /MODE
PRELOAD	/Q0 /Q1 /Q2 /Q3 /Q4
CHECK /Q0 /Q1 /Q2 /Q3 /Q4
CLOCKF CK ; should be 00001
CHECK /Q4 /Q3 /Q2 /Q1 Q0
CLOCKF CK ; should be 00010
CHECK /Q4 /Q3 /Q2 Q1 /Q0
CLOCKF CK ; should be 00011
CHECK /Q4 /Q3 /Q2 Q1 Q0
CLOCKF CK ; should be 00100
CHECK /Q4 /Q3 Q2 /Q1 /Q0
CLOCKF CK ; should be 00101
CHECK /Q4 /Q3 Q2 /Q1 Q0
CLOCKF CK ; should be 00110
CHECK /Q4 /Q3 Q2 Q1 /Q0
CLOCKF CK ; should be 00111
CHECK /Q4 /Q3 Q2 Q1 Q0
CLOCKF CK ; should be 01000
CHECK /Q4 Q3 /Q2 /Q1 /Q0 
CLOCKF CK ; should be 01001
CHECK /Q4 Q3 /Q2 /Q1 Q0
CLOCKF CK ; should be 01010
CHECK /Q4 Q3 /Q2 Q1 /Q0
CLOCKF CK ; should be 01011
CHECK /Q4 Q3 /Q2 Q1 Q0
CLOCKF CK ; should be 01100
CHECK /Q4 Q3 Q2 /Q1 /Q0
CLOCKF CK ; should be 01101
CHECK /Q4 Q3 Q2 /Q1 Q0
CLOCKF CK ; should be 01110
CHECK /Q4 Q3 Q2 Q1 /Q0
CLOCKF CK ; should be 01111
CHECK /Q4 Q3 Q2 Q1 Q0
CLOCKF CK ; should be 00000
CHECK /Q4 /Q3 /Q2 /Q1 /Q0
SETF MODE
CLOCKF CK ; should be 00001
CHECK /Q4 /Q3 /Q2 /Q1 Q0
CLOCKF CK ; should be 00010
CHECK /Q4 /Q3 /Q2 Q1 /Q0
CLOCKF CK ; should be 00011
CHECK /Q4 /Q3 /Q2 Q1 Q0
CLOCKF CK ; should be 00100
CHECK /Q4 /Q3 Q2 /Q1 /Q0
CLOCKF CK ; should be 00101
CHECK /Q4 /Q3 Q2 /Q1 Q0
CLOCKF CK ; should be 00110
CHECK /Q4 /Q3 Q2 Q1 /Q0
CLOCKF CK ; should be 00111
CHECK /Q4 /Q3 Q2 Q1 Q0
CLOCKF CK ; should be 01000
CHECK /Q4 Q3 /Q2 /Q1 /Q0 
CLOCKF CK ; should be 01001
CHECK /Q4 Q3 /Q2 /Q1 Q0
CLOCKF CK ; should be 01010
CHECK /Q4 Q3 /Q2 Q1 /Q0
CLOCKF CK ; should be 01011
CHECK /Q4 Q3 /Q2 Q1 Q0
CLOCKF CK ; should be 01100
CHECK /Q4 Q3 Q2 /Q1 /Q0
CLOCKF CK ; should be 01101
CHECK /Q4 Q3 Q2 /Q1 Q0
CLOCKF CK ; should be 01110
CHECK /Q4 Q3 Q2 Q1 /Q0
CLOCKF CK ; should be 01111
CHECK /Q4 Q3 Q2 Q1 Q0
CLOCKF CK ; should be 11111
CHECK Q4 Q3 Q2 Q1 Q0
CLOCKF CK ; should be 11110
CHECK Q4 Q3 Q2 Q1 /Q0
CLOCKF CK ; should be 11101
CHECK Q4 Q3 Q2 /Q1 Q0
CLOCKF CK ; should be 11100
CHECK Q4 Q3 Q2 /Q1 /Q0
CLOCKF CK ; should be 11011
CHECK Q4 Q3 /Q2 Q1 Q0
CLOCKF CK ; should be 11010
CHECK Q4 Q3 /Q2 Q1 /Q0
CLOCKF CK ; should be 11001
CHECK Q4 Q3 /Q2 /Q1 Q0
CLOCKF CK ; should be 11000
CHECK Q4 Q3 /Q2 /Q1 /Q0 
CLOCKF CK ; should be 10111
CHECK Q4 /Q3 Q2 Q1 Q0
CLOCKF CK ; should be 10110
CHECK Q4 /Q3 Q2 Q1 /Q0
CLOCKF CK ; should be 10101
CHECK Q4 /Q3 Q2 /Q1 Q0
CLOCKF CK ; should be 10100
CHECK Q4 /Q3 Q2 /Q1 /Q0
CLOCKF CK ; should be 10011
CHECK Q4 /Q3 /Q2 Q1 Q0
CLOCKF CK ; should be 10010
CHECK Q4 /Q3 /Q2 Q1 /Q0
CLOCKF CK ; should be 10001
CHECK Q4 /Q3 /Q2 /Q1 Q0
CLOCKF CK ; should be 10000
CHECK Q4 /Q3 /Q2 /Q1 /Q0
CLOCKF CK ; should be 00000
CHECK /Q4 /Q3 /Q2 /Q1 /Q0
TRACE_OFF




Regards,

E.M.