🚀 go-pugleaf

In article <65200006@hpl-opus.HP.COM>, jewett@hpl-opus.HP.COM (Bob Jewett) writes...

>> I want to put together a frequency synthesizer (square wave)
>> that can adjust between 1 and 10 MHz with 255 steps (ie. 35k Hz
>> per step).
> 
>Frequency synthesizers have lots of other specs that you don't mention,
>such as jitter (phase noise), tuning speed, phase windup, ...
> 
>> The PLL's I've looked at don't have the range, synthesizers
>> don't have the speed (500k Hz max.)
The Motorola MC4024P has a maximum frequency of 15 Mhz at
the specified temperature range and a maximum frequency of
25 Mhz at room temperature.
> 
>The PLL only needs an octave of tuning range.  Get the rest with a selectable
>number of binary dividers on the output.
The spec sheet for the MC4024P shows how to use a multiplexer
to use the two VCOs on the chip (each with a tuning range of
3.5:1) to get a range of 10:1.  The example shown is an
application where a 1-10 Mhz VCO is needed.
> 
>> Ideas???
Of course another way of doing it is to use the direct digital
sythesis method mentioned in a previous article.  It can be
done using discrete TTL chips.  A 1984 (i think) QST article
describes just such a generator using 74F series chips, an EPROM,
and a video speed D/A converter available from TRW for about
$52 (at that time).  The performance was impressive with
a range of 1hz to 6.5 Mhz in 1 hz steps.  Stability was solely
a function of the crystal oscillator.  I believe kits are still
available for this device in the $450 dollar range (assembled and
tested I think).

In January '87 (when I was home with mono)  I built a scaled down
version of this thing for about $50.  The performance is very good.
It has a range of 0.25 hz to 1.6 Mhz in 0.25 hz steps.  There are
some spikes on the output (due to a slight design oversight) on
some of the higher frequencies, but I was able to zero-beat WLS
xhicago at 980000009.5 hz although that 9.5 may be the crystal's
error on my end.

The thing isn't that hard to build (I used wirewrap) and the parts
are fairly cheap.  The problem is that the clock must be 2.5 times
the maximum frequency you intend to generate and the logic must
have a propagation delay appropriate to that clock rate.
The idea is fairly simple too.  It uses a 24 bit adder fed into
a 24 bit latch feeding one of the adder inputs.  The latch is
clocked at 2**24 hz (or in my case 2**22 hz i.e. 4.194 Mhz)
the other adder input is controlled by a computer which does
the sole function of converting decimal to 24 bit binary.
the output of the latch goes to an eprom lookup table which uses
the top 8 bits to look up a sinewave.  The output of that goes
to the video speed D/A encoder.  I used a 3-8 decoder using the to 3
top 3 bits going to four transistors which turn on  four resistors
which form a voltage divider with the 75 ohm resistor accross the out
output.

Clocking a 12 bit adder/latch combination at 25 Mhz will yield
yield 6 khz to 10 Mhz in 6.103 khz steps.  This means the logic
must run with a clock period of 40 ns.  I think two 74F374's and
three 74F283's will just BARELY do this, maybe not.  If not,
it is possible to buy several and select the fastest ones
by trial and error.  Increase the clock speed until the most
significant bits go goofy.
> 
>For ideas, I'd go for maintenance manuals of commercial frequency
>synthesizers.
Or a book on pll's by Howard M. Berlin.  I bought my copy in the
late 70's so I don't even know if it's still in print.  For the
last two weeks I have been building a synthesizer with a range
of 1.2Mhz to 4.77 Mhz in 100 hz steps. performance is poor as
far as stability, although I may have something wrong, not
enough shielding in the loop filter or some other silly problem.
It's fine for testing L/C circuits but for crystal filters
(the reason it was built) the performance is not good enough (yet)
> 
>Bob
good luck,
--Brad