🚀 go-pugleaf

In article <1992Nov12.222122.12200@nntp.hut.fi> sakaria@vipunen.hut.fi (Sakari Aaltonen) writes:
>In article <1dnt1fINNk0f@uranium.sto.pdb.sni.de> Josef Moellers <mollers.pad@sni.de> writes:
>>You don't need any provisions for a cache, i.e. none in particular.
>>All You need is a means to temporarily suspend operation of the CPU
>>while You process a cache miss.

>Yeah, well, I do know in a general way how caches operate. What I
>don't know is how they are implemented with a 68000. What kind of
>hardware will do the job, that sort of thing. Are any IC's available
>for the purpose, for example? What do the accelerators use? I've
>never seen one...

Many of the dynamic RAM controller chips can do this.  It's been a while,
so I don't remember the numbers.  This is the same as in the 80?86 community,
so if you can find a 386 with caching (say), you can find out some of the
part numbers.

Should point out, however, that if you're talking about disk caching (or anything
else that requires CPU intervention) that you can't do it without a lot of
grief.  The MC68000 has no way to save memory access state, so cannot be
used to service the cache miss.  The MC68010 and above *do* have this
capability.  (In essence, the 68000 doesn't have instruction restart or
continue)

Back in the old days, if you wanted to do demand paging with a 68000, you
had to put the 68000 into HALT, and have an auxiliary processor wake up,
service the page fault, and unHALT the 68000.  Obviously, you don't
get to timeslice processes during the fault processing...