🚀 go-pugleaf

In article <1992Dec14.054100.13939@athena.cs.uga.edu> mcovingt@aisun3.ai.uga.edu (Michael Covington) writes:
>Phase-locked loop with divide-by-2 in the feedback loop?
>74HC4046 and a flip-flop, perhaps...

Too complicated. If you just want to double a digital clock, use an inverter
to create a pulse with a positive or negative edge. Then use a short time
RC network to reset a flip flop. Since you only need pulses anyway, trigger
the circuit on both the positive and negative going pulses and you got
yourself a frequency doubler. If you actually want 50/50 duty cycle, then
the PLL route is the best way to go.

An example of triggering on both pulses is in Art of Electronics, but I don't
have my copy with me, so I can't draw the circuit out without some effort.
Wasn't too complicated as I remember anyways.