🚀 go-pugleaf

Well here's what I have so far. One real meaty response:

--------------------- Included text follows ----------------------------
--------------------- [ My notes in brackets ] -------------------------

Legend:

>> [Byron]
>  [John West]

******
[Byron's additional comments, questions, and suggestions]
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>
>DRAMs use a capacitor to store each bit. Because the capacitors leak, they have
>to be refreshed. SRAMs use a flip-flop circuit to store the data. This is
>faster, requires no refresh, but unfortunately takes 4 times the chip area
>(this is why SRAMs are usually 1/4 the density of DRAMs).
>PSRAMs are really DRAMs, but they have all the DRAM controlling and refreshing
>circuitry built in. They get the density of DRAMs with the ease of use of SRAMs
>Random access cycles tend to be fairly slow. (I've got data on Hitachi's
>HM658512 512K*8 PSRAM. Random access for the -8 part is 160ns. For addresses
>within the same column (high 8 address bits the same), the access time is 80ns.

***************
AHA! I knew that there wasn't something for nothing. The part number you
quoted maybe the part I've found. So in essense it's an 80ns page mode (or
static column, I could never tell the difference) 4 Mbit Dram with built-in
refresh....

Are you sure about the 8 high bits? So the RAM is asymettric (8 rows and 11
columns)? I'll take 2K columns if that's really the case because I can keep
the RAM asserted until I switch to a new page on them. Giving me 80 ns
access time for all but the first access of a page. Hmmmm.

[ I got ahold of the data sheet for the Toshiba part that Microprocessors sells.
  It has some differences. Random access cycle time is 130ns 
  (80ns access and 50ns precharge). What John says about same column 
  addressing doesn't seem to be correct. While the column is the 8 high bits 
  (11 row bits), from the block diagram I saw it looks like you get same row 
  access not same column. A row (11 bits) seems to select a 256 x 8 block of 
  the RAM and sends it to the sense amps and column select logic. Once a row 
  is selected you can change the column and collect the same row-selected data.
  It seems that to get max efficiency you must wire the chip addresses 
  backwards! ]


***************
>
>>1. Packaging - 19 Address, 8 data, 2 power, 1 read/write, and 2 chip selects
>>               can fit in a standard 32 pin DIP. Since it's an odd number of
>>               address lines pseudo-statics are probably not multiplexed.
>>               Is this correct?
>
>This is correct. 19 address lines gets you 2^19=524288 bytes.

***************
Good.

[ Almost JEDEC standard for 32 pins. Normal 32k x 8 on the lower 28 pins, 
  A18 on pin1, A16 on pin2, A17 on pin 30 , A15 on pin 31  ]
***************

>
>>2. Refresh   - Must psuedo-statics be refreshed like dynamics? If so how is it
>>               done? How often must it be done?
>
>The chip handles refreshing itself. Well sort of. You have to pull /OE low
>while /CE is high occasionally (this triggers a refresh cycle), but it takes
>care of address generation and all the rest.

***************
Ok. I can handle that. My system has 2 processors (the 68040 for computation,
and a 68340 for I/O.) The '340 has many timers (including a dedicated periodic)
that can be set to do hardware refresh. The question is how often does this
(/OE asserted, /CE negated) cycle have to happen to keep the RAMs happy? I think
normal DRAMS are all rows every 4ms. Are the PSeudo- statics the same?

[NOT! While the pulling the OE low is correct you'll be glad to know that the
 refresh cycle of these puppies is (get this) 32 ms! WHOA! you have to pulse
 the OE line 2048 times in that period to keep it refreshed. It has all the
 counters and whotnot built-in. There are 3 types of refresh with one involving
 CE and the other 2 OE. Couldn't really tell the diff between the 2 OE 
 refreshes.]
***************

>
>>3. Access time - Does pseudo-statics require a precharge like dynamics? This
>>                 precharge effectivly halves the bandwidth of dynamics. 
>
>Yes, but that is hidden. From the outside, it looks like a slow SRAM. If you're
>staying within the same column, the access time halves for all but the first
>cycle.

***************
[ The Toshiba part had 1/2 clock (40-50ns) precharge with 130ns cycle time. I
  can most definitely live with that for a whopping 2 Mbytes of memory for $108
]
***************

>
>>4. Standby   - Most low power statics can retain info down to 2V at microamp
>>               power. Can pseudo-statics do the same thing?
>
>No. Its a DRAM, which must be refreshed. But while /CE and /OE are high, it
>is in 'Standby' mode, with 200 or 350 uW (depending on the version) power
>consumption. Active, it takes 250mW.

***************
I'm assuming this is at 5V? What is the minimum acceptable Vcc?

[ Minimum Vcc is 4.5V (5V +- 10%). You can get 200 uA (not uW) standby by 
  pulling CE and OE close to the power rail. The nice thing is that the OE
  only refresh cycle takes the same amount of current (200 uA).  ]
***************

John, you're a lifesaver. I'll order these just as soon as I get the part
number. I hope we can talk some more because there is only slightly more
effort necessary to use these Pseudo-statics as opposed to real static
RAMS. 

[ After looking at the data sheets I find this to be even more true. Imagine
  an 8051 or 68HC11 with only one of these parts. 512K bytes to play with!
]


>
>Anyway. I have the databook here (Hitachi). If you want any info, just yell.
>
> John West
> -- 

-----------------------------End included text --------------------------------

So that's it. Execept for the refresh they look like a 512K x 8 130ns static
RAM. They have low enough standby current that they can be battery backed.
It is really too good to be true. I'm putting in my order tomorrow.

[ I ordered and received 8 parts. They look just like 128K x 8 statics. I plan
  to start using them this week. Because of the 200 uA power consumption I'm
  going to attempt to build a 2 Meg  RAM disk using some Radio Shack heavy-duty
  rechargables (4.3 Amp-hours!). My off the cuff estimate predicts that 4 RAMS
  and overhead circuitry can be powered for like 18 weeks! WOW! 
  Keep you posted. ]

Later,

BAJ
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Another random extraction from the mental bit stream of...
Byron A. Jeff - PhD student operating in parallel!
Georgia Tech, Atlanta GA 30332   Internet: byron@cc.gatech.edu