🚀 go-pugleaf

In article <1992Dec15.023603.27256@cc.gatech.edu> byron@cc.gatech.edu (Byron A Jeff) writes:
>>> [Byron]
>>  [John West]
>[Byron's additional comments, questions, and suggestions]
>>Random access cycles tend to be fairly slow. (I've got data on Hitachi's
>>HM658512 512K*8 PSRAM. Random access for the -8 part is 160ns. For addresses
>>within the same column (high 8 address bits the same), the access time is 80ns.
>AHA! I knew that there wasn't something for nothing. The part number you
>quoted maybe the part I've found. So in essense it's an 80ns page mode (or
>static column, I could never tell the difference) 4 Mbit Dram with built-in
>refresh....
>
>Are you sure about the 8 high bits? So the RAM is asymettric (8 rows and 11
>columns)? I'll take 2K columns if that's really the case because I can keep
>the RAM asserted until I switch to a new page on them. Giving me 80 ns
>access time for all but the first access of a page. Hmmmm.

I don't think you're reading the data sheet correctly. The HM658512
devices does not have a "page" mode. All accesses take the same amount
of time, 80 ns from when CE* goes active. Then you must precharge the
device for 40 ns (tp), and allowing 5 ns each for CE* rise and fall
time, the cycle time is a minimum of 130 ns. (precharge is required
for ALL cycles, not just those that are not "in-page".)

Also, this part does not act like a "real" SRAM because the address
is latched on the falling edge of CE*. Changing the address during
CE* low has no effect, the address is only loaded during the falling
edge.

Aside from that, it's a cute part if you don't want to use a real DRAM.

>[ The Toshiba part had 1/2 clock (40-50ns) precharge with 130ns cycle time. I
>  can most definitely live with that for a whopping 2 Mbytes of memory for $108

This sounds like the Hitachi part also.

-- 
My opinions are my own.