🚀 go-pugleaf

In article <1992Dec16.011918.25341@eng.ufl.edu> iqbal@omaha.eel.ufl.edu (M.Iqbal) writes:
>In article <1992Dec12.003507.1@research.ptt.nl>, walvdrk_r@research.ptt.nl (Kees van der Wal) writes:
>|> In article <1g4ul8INN2em@violet.csv.warwick.ac.uk>, esrej@csv.warwick.ac.uk (Mr
>|> L A J Davis) writes: 
>|> 
>|> > I purchased a 486 motherboard fitted with a 486DX2 50MHz cpu. Unfortunately
>|> > ... stuff deleted
>
>Square wave have infinte number of frequencies: a fact explained in 
>any introductory communication book. If you do not believe me than 
>try finding Fourier Transform of a pulse train or see a specturm
>of a pulse train on a spectrum analyzer. 

Actually I was under the impression that a square wave only had
odd harminics. That's what we see in communications  and
signal processing textbooks.

>
>Anyways, one should be able see that square wave have harmonics all over 
>the frequency band. What CPU is doing is picking up a harmonic of the input
>clock frequecny. Therefore, second harmonic of 25 mhz is 50 mhz and similarly
>second harmonic of 33 mhz is 66 mhz. Usually, a CPU has a Phase lock loop
>to lock on the second harmonic of the clock frequency; thus, running 
>the internal circuitry of the porcessor at 50 or 66 mhz. One can, however,
>pick up second harmonic by using a filter, but, it is much easier to build 
>a Phase lock loop on a silicon wafer than passive components like R, L, 
>and C.

I seems far mor likely they are using both edges of the clock to generate
a frequency doubled clock. The optimum duty cycle with a high performance
VLSI device is seldom %50 so a PLL approach probably wouldn't be
suitable anyways.

Ken Mikolajek.
mikolaje@ccrs.emr.ca