🚀 go-pugleaf

Hi,

	I have a circuit in which I'd like a latch to maintain its value
when a state machine isn't in a certain state, and to acquire new data when
the state machine is in a certain state.  I would think that doing the
following would suffice:

	Out.d=Out&!In_Magic_State#Latch_Me&In_Magic_State

	This is in CUPL syntax, and In_Magic_State would expand to look
something like S2*!S1*!S0, meaning that it would be true in state 100.

	The problem is that this doesn't work.  The latched output goes
high for one clock cycle if Latch_Me is high, but then always dives back to
zero on the next clock cycle.

	So far I've tried added a #Out&In_Magic_State on the off chance
that there was a static hazard floating around, but this didn't help.

	I haven't yet tried this circuit at slow speeds, but I will
soon.  Even so, I'm using 25ns GALs with about a 500kHz clock -- not
exactly blindingly fast.

	What's strange is that if I actually go to the trouble to properly
design the above equation as a state machine (i.e., specify both outputs 0
and 1 as states and specify how you get from one to another), the thing
works.  The logic equation produced by this approach is different than the one 
above, but it's hard to tell exactly what the difference is since the GAL has 
inverted outputs and Demorgan's Theorem has been distributed over whatever 
final equation was used (in other words, the end equation looks little like the 
beginning equation).

	So... can someone tell me that the above equation really should
work, and that something else is getting screwed up somewhere?  Or better
yet... do you know which equation would work?  (And why?)

	Thanks...

						---Joel Kolstad
						kolstad@cae.wisc.edu