Article View: sci.electronics
Article #15650Electronics Design Question
From: David J Madura
Date: Wed, 30 Dec 1992 22:25
Date: Wed, 30 Dec 1992 22:25
18 lines
1266 bytes
1266 bytes
Well I've scanned my .newsrc for an appropriate group to place this question and I came up with this one, if it belongs somewhere else please let me know. I have a circuit design that I need integrated down to 1 or 2 chips using FPGA,PLD's or what have you. I don't know much about custom or semi-custom chips to know what would be the most cost-effective. The circuit is input a 24-bit address and must compare it against 4 loadable 24-bit address and raise or lower one of four corresponding chip select lines. It must do this withing 35 ns at least. So the chip must have at least 24 input lines and 4*24=96 flip-flops . I can't do this with discrete components and must have it in one chip because of size considerations. My question is what would be the most cost-effective way of realizing this?
Technical Details
Message-ID:
<1238@blue.cis.pitt.edu>Path:
arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!news.sei.cmu.edu!drycas.club.cc.cmu.edu!pitt.edu!djmst19Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!cis.ohio-state.edu!news.sei.cmu.edu!drycas.club.cc.cmu.edu!pitt.edu!djmst19 Newsgroups: sci.electronics Subject: Electronics Design Question Message-ID: <1238@blue.cis.pitt.edu> From: djmst19+@pitt.edu (David J Madura) Date: 30 Dec 92 22:25:08 GMT Sender: news+@pitt.edu Organization: University of Pittsburgh Originator: djmst19@unixd3.cis.pitt.edu Lines: 19