Article View: sci.electronics
Article #16064Re: ECL logic computers ?
From: Edwards Thomas G S1A x8297
Date: Fri, 28 Jun 1991 15:32
Date: Fri, 28 Jun 1991 15:32
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In article <2045@ole.UUCP> ssave@ole.UUCP (Shailendra Save) writes: >From article <2544@cluster.cs.su.oz.au>, by rex@cs.su.oz (Rex Di Bona): > I think that the prime reason that people are not designing in > ECL is because of power-dissipation problems. At very high > frequencies, CMOS power dissipation will also be too high. I use subthreshold CMOS (i.e. Vds < 1.5V) to avoid power dissipation problems with analog circuits. Does anyone know of subthreshold CMOS FET digital logic design? I imagine noise would be an immense problem, but use of fault-tolerant design may enable this to be a reasonable high-speed design method. Besides, it doesn't require any special device technology, just special CMOS design. -Tom
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arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!aplcen!aplcomm!tedwardsReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!aplcen!aplcomm!tedwards From: tedwards@aplcomm.JHUAPL.EDU (Edwards Thomas G S1A x8297) Newsgroups: sci.electronics Subject: Re: ECL logic computers ? Summary: Subthreshold Digital? Message-ID: <471@aplcomm.JHUAPL.EDU> Date: 28 Jun 91 15:32:13 GMT References: <2544@cluster.cs.su.oz.au> <2045@ole.UUCP> Reply-To: tedwards@aplcomm.jhuapl.edu (Edwards Thomas G S1A x8297 ) Organization: JHU/APL, Laurel, MD Lines: 14