🚀 go-pugleaf

>
> I use subthreshold CMOS (i.e. Vds < 1.5V) to avoid power dissipation
> problems with analog circuits.  Does anyone know of subthreshold
> CMOS FET digital logic design?  I imagine noise would be an immense
> problem, but use of fault-tolerant design may enable this to be
> a reasonable high-speed design method.  Besides, it doesn't require
> any special device technology, just special CMOS design.
>

Haven't heard of any, but I would assume it would be because it would be dog
slow.  To the best of my knowledge, subthreshold opamps / OTAs are used 
where you need ridiculously low power consumption and aren't concerned about
bandwidth (correct me if I'm wrong - it's been a couple of years since I've
designed analog at the chip level).  At low speeds, normal CMOS logic uses
practically no power.  However, the push towards a ~3V (3.3V?) logic
standard promises lower power consumption at high speeds (remember, power
dissipation in CMOS logic is proportional to C*V^2*f).
Unfortunately, the lower Vdd will also make the logic more suceptable to
induced noise. We may be looking at the last gasp of single-ended
(as opposed to differential) electronic logic.

Andy