🚀 go-pugleaf

Application Specific Integrated Circuits (ASICS) are developed using a semi-custom
design style (prepackaged building blocks).  Virtually any custom design can
theoretically be done as an ASIC design.  Below outlines the steps necessary to
produce an ASIC design.

	1) Design Architecting
		This is usually performed with schematic capture tools, however
		it is possible to enter a design textually.  Certain high level
		functions may require cell compilation (RAMS, ROMS, PLAS,
		Multipliers, etc.) tool, and are usually supplied by the silicon
		vendor (for a hefty fee).

	2) Design Verification
		This requires simulation tools, electrical rules checkers, and
		possibly timing analysis tools.  Wiring parasitics should be
		estimated at this stage and included in the description, if not
		the timing margins should be made extremely conservative.

	3) Design Layout
		This is usually done by an automated package.

	4) Post-Layout Verification
		The same tools are run as in the Design Verification phase, only
		the actual wiring parasitics are included.  Steps 3 and 4 may need
		iteration until the design specifications are met.

	5) Test Program Generation
		This requires a good understanding of testing methodology.  Some
		vendors may require fault coverage analysis (fault simulation) on
		your design.

	6) Manufacturing

	Typically, a commercial vendor requires at least $50,000 (USD) as a NRE
	(non-recurring engineering) expense.  Each mask manufactured may cost up
	to $1000 (there are processes that require approx. 20 mask levels).  A
	commercial setup for design usually runs in the $100,000.

	Now that I have scared you away, there are some less expensive options:

		1) FPGA (field programmable arrays)
			Similar to designs created using a gate-array approach,
			they allow you to program the functionality (including
			sequential operations).  It also alleviates the need for
			developing a test program, as the device can be tested
			in the application system.

		2) The MOSIS project.
			This project allows a group of designers to share the
			costs of manufacturing.  Instead of a single design per
			wafer, a number of designs are placed on the wafer.  MOSIS
			was created to allow University students to manufacture
			designs at low cost.  There are a number of University tools
			available (SPICE, MAGIC, etc.) that are available with
			MOSIS libraries.  I suggest you contact your local
			University's Electrical Engineering department if interested.

	As for your chip that creates hsync and vsync from a clock.  I did this in an
	ASIC for RCA back in 1979 (before the term ASIC was born).  I am confident
	that it can be done today (the tricky part was, if I remember, generating
	the proper delay lines), However, I would be suprised if it weren't already
	available commercially, these devices are called sync generators.

	Gary