🚀 go-pugleaf

A what-if question;

I'm designing a memory controller to interface to the 80C188EA. According
to the timing diagrams, there a three cycle status bits S(2:0) which are
valid before the T1 state. The read or write command is valid during the
T2 state. My question is this; if I know what kind of cycle I'll be 
performing even before the command is given, can I let my memory state
machine just look at these status bits when I latch the address, instead
of waiting around for the command. 

- tjl