🚀 go-pugleaf

  If you're not concerned about duty cycle, I'd recommend an edge detector
instead.  It's an X-OR gate, with the clock fed into one input, and a
delayed version of the clock into the other.  The output is a pulse train,
with a pulse occurring for each clock edge that is as wide as the delay
used on the input.

  Example:

	      +------+      +------+      +-----
IN	------+      +------+      +------+    

	      +-+    +-+    +-+    +-+    +-+
OUT	------+ +----+ +----+ +----+ +----+ +---

  The interval between output pulses is a function of the input duty cycle;
interpulse intervals will be equal only for a 50% DC input.