🚀 go-pugleaf

Does out there know about new wafer scale integration research?  It
seems to me that it just would not be so hard to make an arbitrary
permutation interconnection type computer that would allow at least
128 good dies to be switched into a hypercube-like network on a single
CMOS wafer.  A simple two address risk processor with a small local
ram should easily run at 20 to 40 MIPS if it were an accumulator
machine, so the processing power could be astounding.  The wafer
should be about the most reliable thing around, because new processors
could be switched into the network after a processor dies.  The
switching network itself would also be very reliable... IBM has
researched the idea of reliable arbitrary permutation networks and
came up with a beautiful solution, although it is designed only to
work if 32 out of 33 chips work in each of two rows of chips.  I think
it could be modified to work with die yields of only 50% in the
interconnection dies.  If there is a simple solution to the heating
problem, like gluing the wafer to a water-cooled block of some type of
ceramic, and using a muffin fan to cool the water, then it seems like
the whole thing would fit into something the size of an Apple II
computer.

Its frustrating to work at a company that probably could manufacture
such wafers, but is to inflexible to think about such ideas.  Is there
any kind of research of this sort going on somewhere else?

Bill Cox
ucbvax!voder!wdcox
National Semiconductor