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Article #17225Re: wafer scale integraion, anyone?
From: billw
Date: Fri, 30 Jan 1987 22:00
Date: Fri, 30 Jan 1987 22:00
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1176 bytes
Several heavilly funded companies (eg Trilogy) have attempted to do wafer scale integration, and failed due to technical problems. It isn't easy - remember that your "arbitrary interconnect" to connect the good processor dies has to have its own redundancy, and that for large N, interconnects are more complicated than processors anyway. There was an artical in Electronics or digital design or some such reporting on one of the few companies left, who have succedded in making memory chips out of large pieces of wafers - unfortunately, the total capacity is less than some memory chips produced by more conventional means. BillW
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Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: arc1-ca.pugleaf.net!utzoo!watmath!clyde!rutgers!sri-spam!sri-unix!hplabs!decwrl!labrea!navajo!billw From: billw@navajo.UUCP Newsgroups: sci.electronics Subject: Re: wafer scale integraion, anyone? Message-ID: <1356@navajo.STANFORD.EDU> Date: Fri, 30-Jan-87 17:00:24 EST Article-I.D.: navajo.1356 Posted: Fri Jan 30 17:00:24 1987 Date-Received: Sat, 31-Jan-87 16:02:45 EST References: <2841@voder.UUCP> Organization: Stanford University Lines: 14 Summary: it isn't easy