Article View: sci.electronics
Article #19387Re: Vero-wire circuit prototyping system
From: Andreas Nowatzyk
Date: Fri, 08 Jul 1988 06:12
Date: Fri, 08 Jul 1988 06:12
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I used Vero-wire and a similar technology distributed by Siemens for a system with more than 1000 standart TTL chips (arround 1978!) running at 10 Mhz. No problem. However, using today's faster logics (F, AS,...) will cause problems. All wires run in rather crowded channels and cross-talk becomes a problem. Also, you have to have reasonably good solder skills. PWR and GND must be dealt with by other means. Also, this method is not as fast as wire-wraping, but way cheaper. -- Andreas -- -- Andreas Nowatzyk (DC5ZV) Carnegie-Mellon University Arpa-net: agn@unh.cs.cmu.edu Computer Science Department Usenet: ...!seismo!unh.cs.cmu.edu!agn
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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!lll-winken!lll-lcc!ames!ll-xn!mit-eddie!bbn!rochester!pt.cs.cmu.edu!unh.cs.cmu.edu!agn From: agn@unh.cs.cmu.edu (Andreas Nowatzyk) Newsgroups: sci.electronics Subject: Re: Vero-wire circuit prototyping system Keywords: vero wire prototype Message-ID: <2203@pt.cs.cmu.edu> Date: 8 Jul 88 06:12:28 GMT References: <187@lithium.kcl-cs.UUCP> Sender: netnews@pt.cs.cmu.edu Organization: Carnegie-Mellon University, CS/RI Lines: 14