Article View: sci.electronics
Article #20143Re: I2C Bus
From: Sun NCAA
Date: Wed, 07 Dec 1988 20:23
Date: Wed, 07 Dec 1988 20:23
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Its an interchip serial communications protocol. Think of it this way. Most
CPUs talk to their chips in a parallel fashion. The more chips there are, the
pins there are, the more board real-estate is consumed to hold the chips. Now
consider the devices you've mentioned. They really don't require the higher
processing speed provided by parallel interchip communications, and they
certainly could use a reduction in board real-estate. Sooner or later someone
had to come up with a way for chips to talk serially. In steps Signetics/Philips
with their "I2C bus" and "I2C bus compatible ICs".
--
Matthew Lee Stier (919) 469-8300|
Sun Microsystems --- RTP, NC 27560| "Wisconsin Escapee"
uucp: {sun, rti}!sunpix!matthew |
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!xanth!mcnc!rti!sunpix!matthew From: matthew@sunpix.UUCP ( Sun NCAA) Newsgroups: sci.electronics Subject: Re: I2C Bus Message-ID: <290@greens.UUCP> Date: 7 Dec 88 20:23:09 GMT References: <1404@thumper.bellcore.com> Organization: Sun Microsystems, Research Triangle Park, NC Lines: 16