🚀 go-pugleaf

It has come to my attention that there was a poting in sci.electronics
by John Logajan some time ago, which needs to be answered.
From: lee@toad.pilchuck.Data-IO.COM (Kyu Lee)
Path: toad!lee

John Logajan states:

> This is a comment I made in usenet news sci.electronics:
> We use Dash and Abel here at Network Systems.  I like the ability of being
> able to draw a schematic of the guts of my PLD.  In fact, our company is
> considering making the schematic of PLD's the prefered documentation method.
> 
> Thus we are interested in the advertised "FutureDesigner" product which is
> claimed to be able to produce schematic drawings from logic equations --
> a feature that would allow us to schematically document hundreds of PLD's
> that already exist here.
> 
> Unfortunately, we haven't been able to get a demo of this alleged product
> from our local Data-I/O rep -- yet.  I am tempted to suspect that it is
> still in the vaporware stage.

FutureDesigner is not a vaporware;  it has been out in the marketplace
for some time.  I will have someone contact you.  If you still do not
get a satisfactory response, let me know.
If we have not been responsible to respond to your needs, please
accept my apology.  But then, how did you try?  If you let us know,
we will fix the problem (of communicating).  I am cc-ing this
responce, along with your comments to our sales manager.

> 
> The other gripe I have about Dash-Able is that it really falls down on the
> job when it comes to defining macro-cell functions, specifically the
> async-set and reset in 22V10's.  We can't draw it, and are forced to enter
> text into the drawing in the form of equations of weird node names.

This is true.  The product has not been updated for long time,
and we fully understand the problem, and we are addressing that issue,
along with all other PLD synthesis products.  New version of Dash-ABEL
will be out late January, and it should solve the problem you
mentioned.  In fact, if you are interested in being a beta-tester,
please let us know.  In January-February, you will see a drastically
improved DASH-ABLE, improved ABEL (3.1), ABEL-to-XNF for LCA (Xilinx)
design, and PLDTest Plus with major enhancements to PLDTest. 

> 
> I want to do some 20RA10's and I haven't got the slightest clue as to what
> node names to use.
 
 Read my response to the above paragraph.

> 
> Perhaps this is all solved in a latter version.  In this case the lack of info
> flow is due to fault at our end.  So I apologize in advance. 

Yes, these have been solved.  No need for apologies.  We ought to do
better PR to inform our users of these new and great things.  

> 
> - John Logajan @ Network Systems; 7600 Boone Ave; Mpls, MN 55428 -
> - ...rutgers!umn-cs!ns!logajan       or      john@logajan.mn.org -
> 

Kyu Y. Lee
Manager, Logic Synthesis Group
Data I/O Corporation
P.O. Box 97046
Redmond, WA  98073

lee@data-io.com

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