🚀 go-pugleaf

In article <1990Jan30.163700.3520@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
|In article <26414@cup.portal.com> Ordania-DM@cup.portal.com (Charles K Hughes) writes:
|>I am working on an 8MHz 6502/65816 design and I need to know what speed 
|>of DRAM I need.  The spec sheets for the 6502 list a 60ns access time,
|>but I am having trouble believing this when there are 33MHz '386 machines
|>using 80ns drams.  Could somebody explain how this works...
|
|You've discovered Excedrin Headache Number 3.14159 of fast processor design:
|figuring out how to make the memory fast enough to keep up.  386 and 6502
|clock speeds are not directly comparable, so that analogy doesn't hold up.
|An 8MHz 6502 has a 125ns cycle, during which it has to do an entire memory
|access plus overhead (the 386 spreads this over multiple cycles).  Taking
|half the cycle for overhead is a little much, but not grossly implausible
|for a basically low-speed part pushed to higher speeds.

Also, if you're paying lotsa bucks for a 33 MHz 386 system, they'll often
have cache memory in them.  95% of your accesses go into a 25 or 30 ns
64K SRAM.  This might not be easy to add for a 6502/65816, however.  It 
also costs money, just like 60 ns DRAMs.
-- 
		David Chapman

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