🚀 go-pugleaf

In article <19023@crg5.UUCP>, cormack@crg5.UUCP (Mike Cormack) writes:
> [...]
> Think real estate here too. 1 PAL uses much less space than several
> glue logic devices. This can be a crucial in a board design. A reduced
> parts count is always a nice idea and PALs can help out immensely.
> [...]

One thing that bugs me about this is that I can't seem to find any of the
20-pin PALs in surface-mount packages (CMOS would be especially usefull).
In the days of DIPs, squeezing 3 or 5 16-pin DIPs into one 20-pin PAL made
good sense, at least from a space standpoint.  Now, I find it hard to 
justify using a 20-pin DIP PAL when I can fit the same logic in about the
same space using SMT (SMT = Surface Mount Technology) HCMOS.  On a SMT board
we want to avoid through-hole DIPs where possible as additional manufacturing
steps are required, so the PAL has two strikes against it.

Yes, I am aware of the larger PALS in the 28 PLCC (and up) packages, and we
do use them where applicable, but for smaller glue-logic jobs the SMT logic
chips have become more attractive again.  Another reason that random-logic
chips remain a choice is the proliferation of simulation tools in the
workplace.  When PALs hit the world, often a PAL design could be simulated
much more easily than the equivalent discrete logic design.  More than once,
I designed a function with a PAL just to check out the logic, then implemented
it with the equivalent logic chips, because my power budget demanded it.

The die sizes in the erasable PALS (as viewed through the window) look pretty 
big; is this the limiting factor in package size?

If anyone out there knows of an EP310-equivalent functionality part in a SMT
package, let me know.  Even a low-power CMOS 16L8/16R8 would be nice.


-- 
Paul M. Elliott      Optilink Corporation     (707) 795-9444
           {pyramid,pixar,tekbspa}!optilink!elliott
                  "The dog ate my disclaimer."