🚀 go-pugleaf

In article <1992Apr6.033214.15677@resmel.bhp.com.au> jing@resmel.bhp.com.au (Jian Feng) writes:
>>  - On powerup or hard reset, the bottom of the address space should be ROM,
>>    but later on you need at least a few bytes of RAM there. This requires
>>    some switching of address ranges by control signals to the address
>>    recognizer.
>
>Easy. MC68000 reads in the Stack Pointer (SP, the system stack pointer)
>and the Program Counter (PC) from address $0. It takes 4 read cycles on
>the 16b bus. Just use a simple 2 bit binary counter which is reset on
>power-up and on counter-overflow it can switch the address.

However, it is better to use an I/O port bit to control the ROM overlay
because then you can have exception vectors in ROM as well.  This allows
your system to be bulletproof while it is doing the initial RAM diagnostic.
After RAM is certified OK, you can copy the vector table to the RAM image
of the vector table, then throw the bit to turn off the ROM overlay.  Our
systems all work this way, as does the (early, at least) Macintosh.

>>If you want something tricky like zero-wait-state DRAM, then of course it's
>>a nightmare. (How's that implemented, anyway? Does it require software
>>supervision to handle the refresh? I normally use a store-bought DRAM
>>controller chip.)

The 68000 is not very efficient in its bus timing.  It is easy to hide a
memory refresh cycle in the first half of the memory access cycle.  In
fact, a number of 68000 systems (including ours, the toaster Macs, Ataris
and Amigas) run the memory at double-speed and put a video cycle in the
first slot.  As a bonus, video is free (no access time penalty) and refresh
is free (courtesy of the video).  A 7 MHz 68000/68010 only needs 150 nsec
DRAMS in order to do this trick.

Of course, newer members of the 68K family are faster, and won't let you
get away with such 'cute' timing.  C'est la vie.

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