🚀 go-pugleaf

In article <1992Apr15.155915.1515@news.nd.edu> fdeck@sleepy.helios.nd.edu (francis deck) writes:

>I am gearing up to build a "digital sampling oscilliscope"
>which connects to the parallel printer port of an IBM PC.
>My idea is to clock a high-speed flash ADC into a static
>RAM chip.  After a "frame" worth of data are thus collected,
>they are transferred to the PC at lower rate for subsequent
>display, etc.  

>I am looking at the CA3306D converter which can hum along
>at 15 MHz.  So, this will be my target clock rate, with
>lower rates available by dividing the clock down.

        This is probably one of five or six most-often-dreamed-of
projects.  First observation: with a good sample/hold amplifier,
you can up the bandwidth of the input stage without adding error,
and if the input can handle 150 MHz, ten passes can theoretically
be made at staggered intervals after the trigger event, to
fill in the full information.

        Second observation: making a good attenuator/preamp for
the front end of this puppy will be difficult; it might be easier
to make a crude attenuator and use your reference voltage on
the ADC to change by factor of 1/2/5.  Adding a calibration
generator is a good idea (and doesn't take much work).

        Third observation: a dual-trace scope is not twice as
hard as a single-trace; figure on making it modular, so that
adding a channel is a matter of duplicating one small part
of the hardware.

        Fourth observation: a good trigger circuit can be built
with a PLL, and the trigger will have to set off a carefully
timed set of events.  A variety of PLL phase detectors (mixer
type, XOR type, and counter type), and a switch to select
between them, will prove valuable.  Beware skew and delays
in the trigger output; you need ACCURATE timing of the sample/hold
signal, so this signal will have to be driven well, and
terminated carefully.  Using the PLL in lock, you will be able
to view events BEFORE the trigger as well as after.


        John Whitmore