🚀 go-pugleaf

In article <27746@amdcad.AMD.COM> phil@diablo.amd.com (Phil Ngai) writes:
   >
   >AMD has an application brief titled "Minimization of Ground Bounce
   >Through Output Edge-Rate Control", Publication# 10181. 
   >
   > [Phil is] ... posting this ... as a reader of sci.electronics who
   > wanted to share this with the other readers. 


Thanks, Phil, for supplying the pointer above.  However, in my humble
opinion the AMD brief is rather incomplete.  There are other, better,
sources of information on ground bounce:

[1] IDT High Performance CMOS Databook (volume 1 of 2), Application
    and Technical notes, chapter 14.
		"FCT - Fast, CMOS, TTL-Compatible Logic", pp. 14-209..250

[2] EDN magazine, "EDN's advanced CMOS logic ground-bounce tests",
    March 2 1989 issue, pp. 88-114.   {interestingly, some IDT devices
    didn't do well despite their excellent explanations contained in
    reference [1] !!}

[3] Texas Instruments, "Advanced CMOS Logic Designer's Handbook",
    rearcover #SCAA001A.  All of chapters 3 and 4 are good, but the
    best part is page 1-4 and 1-5 (Table 1.1-1 and Figure 1.1-1),
    where they give pin inductance vs pin position for several package
    types.

[4] EDN Magazine, "Equivalent circuits model subtle traits of advanced
    CMOS IC's", by Charles Dike of Signetics Corp.  April 14 1988 issue,
    also available from Signetics.
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 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
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