🚀 go-pugleaf

etxansk@garbo.ericsson.se writes:
> I've been looking at chip descriptions for some common
>memory circuits. 
> There are pins on them named RAS, CAS, and Refresh. I know
>it's basic knowledge, but I'm not sure where to find good
>documentation on this.

Vendor handbooks (like the Intel Memory Handbook) generally have at least
cursory discussions of how refresh works, and certainly tell how to refresh
a given part.

> The RAS and CAS signals are probably input signals to the
>chip used during addressing. I've assumed that they're used
>to tell the chip whether it's the most or least significant
>part of the address vector that's currently on the address
>bus. If I'm right about this, how come there are _two_
>addressing control signals?
> For the Refresh signal: I can't recall if this one really
>is a pin on the chip or if it's some event that's done with
>other signals. I've heard that certain types of chips need
>this signal in order to work properly. What is the CPU (or
>the main clock, or the addressing logic) supposed to do to
>give the memory chips the refresh?

Dynamic RAMs have two addressing signals due to their construction.
Internally, they are laid out as a big square array, and "row address select"
latches which row is addressed and precharges the addressing lines on that
row, and "column address select" chooses one column from that row to
be read out or written.  There are two motivations for this:  it requires
fewer gates to do the decode that would be required for individual selection
(a 1Mb array would require millions of transistors for a one level decode
(one million per-bit transistors plus the decode logic to get that far),
whereas selecting in two 10-bit chunks requires merely thousands of
transistors), and second it makes refresh easy -- selecting  a row refreshes 
all the memory cells on that row, even though only one is eventually selected
for read or write.  You refresh an entire ram by selecting every row at least
once every refresh-time (one to a few milliseconds).  There is no separate
refresh pin on most dynamic rams; some dynamic rams have a special "RAS-only"
refresh cycle that can be used to quickly do refreshes in between regular
cycles; some DRAMs have a "CAS-before-RAS refresh" mode where hitting the
strobes in the "wrong" order triggers an internal refresh cycle from an
internal counter.

As to how refreshing is done, this varies.  The simplest possible
implementation is for the CPU to periodically generate refresh cycles;  you
can interrupt the CPU every millisecond (or several) and have it read N
consecutive addresses, where N is 2^{number of address lines to each DRAM},
if you have set up the row addresses to be the low-order address lines; if
you wire up the memory array properly, one set of DRAMs gets a regular read
refresh, and all the other DRAMs get a RAS-only refresh.  This is great for
low-parts-count systems where timing constraints permit the CPU to take a
few hundred microseconds out every few milliseconds, and where the CPU is
the sole source of memory cycles.

In more complicated systems, it is better to design the memory system as a
whole and have it hide refresh cycles from the outside world.  This is usually
done by having a timer set up with a counter; when the timer goes off, a
refresh cycle is inserted, possibly blocking external access to the RAMs until
it is finished.  A slight improvement is to piggy-back "hidden refresh cycles"
(if supported by the DRAMs) onto externally generated memory cycles (which
would reset the timer) which would reduce the likelyhood of having to hold off
externally generated memory cycles, at the cost of slightly lengthening the
time required for each cycle.

In sufficiently complicated systems, of course, you just buy a DRAM Controller
Chip, program it at boot time with the characteristics of your memory array,
and let it worry about all the details :-).