🚀 go-pugleaf

Given a desire to have N (=5 in this case) I/O port groups
decoded at arbitrary addresses without using a whole boatload
of parts?

My current best, decoding 6 bits (sufficient) is a pair of 74ls138
3->8 demux chips and a jumper field.  This would be ok, except that
the jumper field would take 160 pins to permit truly arbitrary
addressing using regular shorting blocks.

As things stand I've got the jumper field laid out with about 50
pins in such a way that the default configuration can be jumper
selected and so can a few variations of it, but anything very
different would need wire-wrap or soldered jumpers.

I could clearly use a fuse-programmable part to do the job,
but I don't want to make users buy new parts to reconfigure.
Or own an eraser.  Heck, most people don't even own wire-wrap
tools any more.

Any brilliant ideas?  My current best is a small ram or some
kind of content addressible ram, and load it from software
at driver initialization time.  Anybody know of a good chip
for the job?  How about a PAL with a few dozen internal
register bits?

How much effort and what kind of expenses are involved in doing
this sort of thing in an ASIC?  Who would I talk to to get into it?

Thanks.
-- 
Steve Nuchia	      South Coast Computing Services      (713) 964-2462
"To learn which questions are unanswerable, and _not_to_answer_them;
this skill is most needful in times of stress and darkness."
		Ursula LeGuin, _The_Left_Hand_of_Darkness_