Article View: sci.electronics
Article #7901Re: DPLL design needed
From: Dana H. Myers
Date: Fri, 19 Oct 1990 23:02
Date: Fri, 19 Oct 1990 23:02
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In article <1990Oct18.203839.20608@bnrgate.bnr.ca> mleech@bwdlh131.bnr.ca (Marcus Leech) writes: >I need a DPLL design based on the PAL16R8 that can take a NRZI signal > at 1200baud, a clock at 8 or 16 x 1200baud, and generate a > DPLL-LOCKED signal (what this amounts to is a digital DCD). > I'm guessing that there's a reasonably good freeware library of > PAL equations that might contain something like this. Well, if you MUST use the PAL16R8, then the Tucson Amateur Packet Radio 'State Machine DCD' won't help you. Otherwise, the TAPR State Machine DCD is a nice little PC board with a 27C64 OTPROM burned with a state machine program that generates a 'coherent' DCD output. The kit, all parts included, runs about $17 from TAPR. A self clocking option is available for a few dollars more. They're in Tucson, Arizona; try calling information there for their phone number. They accept Mastercard and Visa... /* * Dana H. Myers KK6JQ | Views expressed here are * * (213) 337-5136 | mine and do not necessarily * * dana@locus.com | reflect those of my employer * */
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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!nih-csl!lhc!ncifcrf!haven!purdue!tut.cis.ohio-state.edu!pacific.mps.ohio-state.edu!zaphod.mps.ohio-state.edu!usc!elroy.jpl.nasa.gov!turnkey!orchard.la.locus.com!prodnet.la.locus.com!lando.la.locus.com!dana From: dana@lando.la.locus.com (Dana H. Myers) Newsgroups: sci.electronics Subject: Re: DPLL design needed Keywords: DPLL phase-locked loops NRZI Message-ID: <18518@oolong.la.locus.com> Date: 19 Oct 90 23:02:06 GMT References: <1990Oct18.203839.20608@bnrgate.bnr.ca> Sender: news@locus.com Organization: Locus Computing Corporation, Inglewood, CA Lines: 23