🚀 go-pugleaf

kchen@Apple.COM (Kok Chen) writes:

>kjh@aludra.usc.edu (Kenneth J. Hendrickson) writes:

>>In article <1990Oct31.210242.20619@aplcen.apl.jhu.edu> @aplvax.jhuapl.edu:mjj@stda.jhuapl.edu (Marshall Jose) writes:
>>%I have been trying to understand a passive loop filter I have twice seen used
>>%in ham radio construction articles.  It looks like this:
>>%
>>%
>>%     O---VVVVV----+-------+------O
>>%           R1     |       |
>>%                  |       >
>>%                  |       >  R2
>>%                  |       >
>>%                 ---      |
>>%                 --- C1   |
>>%                  |       |
>>%                  |      ---
>>%                  |      --- C2
>>%                  |       |
>>%     O------------+-------+------O
>>%
>>%
>>%                 C(as + 1)
>>%     H(s) = ---------------------
>>%               3     2
>>%              s  + ps  + qs + r
>>%

>>Your first clue, is that since you have two energy storage devices, that
>>you should have two poles.  When I solve this, I get:

>>                     c1r1 * s + 1
>>H(s) = ---------------------------------------------
>>       c1c2r1r2 * s^2 + (c2r2 + c1r1 + c2r1) * s + 1



>Ken, you forgot the ( K/s ) term of the VCO.  I believe that in 
>Marshall's original posting, he gave the correct closed-loop transfer 
>function

>	H(s) = A(s)B(s)/( 1 + A(s)B(s) )

>where A(s) is the 2-pole filter above and B(s) is the VCO transfer
>function.

>I have always avoided 2nd-order loop filter for precisely this
>reason.  Very hard to estimate what a 3rd-order system would do.
>One of the poles is necessarily real, and it's locus better not 
>fall on the wrong side of the plane.

Agree.  There is another way to look at this.  

1. By eliminating C1 or making it negligibly small, this becomes 
   a first order 'lag-lead' filter.  The resulting second order
   PLL is stable by a properly chosen R2.

2. The above system is characterized by its damping factor d,
   and undamped natural frequency Wn.

		Wn = sqrt ( K / (T1+T2) )	-------- (1)

		d  = Wn * (T2 + 1/K) / 2	-------- (2)

   where	K is the loop gain determined by Kvco and N,
		N being the divide ratio in the feedback loop.

		T1 = R1*C2

		T2 = R2*C2

   The system has optimum unit (phase) step response when d =1.

3. Theoretically we can choose an arbitary Wn (which determines
   the frequency response of the system), calculate T2 by setting
   d = 1 in equation 2, then solve T1 by equation 1.

   Note: If the PLL is programable, K will vary based on the
         operating point of VCO and N value for the feedback
         counter.  d will vary according to K.  Under all situations, 
         d >= 1 must be maintained in order to maintain the
         stability of the loop.

4. But PLL is unique in a way that the phase detector output is
   best modeled by a bipolar pulse train at the frequency of it's
   refernce input.  The amount of 'glitch' attenuation priveded by the
   above lag-lead filter is roughly R1/(R1+R2), which is poor.
   The poorly attenuated phase detector output glitches will
   be translated into phase jitter by the VCO.

5. So how do we deal with this?

   a. Choose a Wn much much less than the reference frequency
      (this produces large T1 + T2).
   b. Follow the steps in #3 to determine T1 and T2.
   c. Now let's introduce a C1 to attenuate the phase detector
      output glitches at the reference frequency.  Since
      the Wn is much much less than the reference frequency,
      R1*C1 can be much less than T1+T2 and becomes negligible
      as assumed in #1.
   d. The best strategy is still a clean VCO and a clean refernce
      input, which will generate pulses with nearly zero pulse width.
      The nearly zero energy associated with nearly zero pulse
      width will reduce the R1*C1 requirement.
 
Jerry Wang (Motorola - Radio Telephone System Group)