Article View: sci.electronics
Article #8212Re: Refreshing DRAM
From: Henry Spencer
Date: Wed, 07 Nov 1990 17:44
Date: Wed, 07 Nov 1990 17:44
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In article <39251@ut-emx.uucp> tjk@ccwf.cc.utexas.edu (Todd Kelman) writes: >>>... They measured and published figures for how much each board >>>slowed down the system, just by being installed... >>Quite possibly because the AT Bus is running at 8MHz, so refreshing that DRAM >>takes longer than refreshing DRAM on the motherboard... > >The problem here stems from the fact that memory refreshing is usually >carried out through DMA cycles... Not quite; memory refreshing *on IBM PCs, clones, and descendants thereof* is usually carried out through DMA cycles. Most real computers do it within the memory circuitry, so that it doesn't need to elbow the processor off the bus, and do all boards/banks in parallel rather than one at a time, so their refresh overhead is independent of memory size. Don't confuse PCs with well-engineered computers; remember, those things were designed at a time when 256KB was a lot of memory. -- "I don't *want* to be normal!" | Henry Spencer at U of Toronto Zoology "Not to worry." | henry@zoo.toronto.edu utzoo!henry
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Newsgroups: sci.electronics Path: arc1-ca.pugleaf.net!utzoo!henry From: henry@zoo.toronto.edu (Henry Spencer) Subject: Re: Refreshing DRAM Message-ID: <1990Nov7.174429.17222@zoo.toronto.edu> Organization: U of Toronto Zoology References: <1445.272CBD1B@ofa123.fidonet.org> <1990Oct31.194436.28242@idt.unit.no> <1990Nov5.063219.2266@research.canon.oz.au> <39251@ut-emx.uucp> Date: Wed, 7 Nov 90 17:44:29 GMT