Article View: sci.electronics
Article #8244Re: Refreshing DRAM
From: Clarence Wilkerson
Date: Thu, 08 Nov 1990 21:22
Date: Thu, 08 Nov 1990 21:22
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This is a little hazy, but a few years back I rewrote the PAL on the Zenith 150 memory board to use 256k chips. I seem to remember that there was a special line to activate all banks during the refresh cycle. I don't have the PAL equations handy to verify this right now.
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arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!noose.ecn.purdue.edu!mentor.cc.purdue.edu!descartes.math.purdue.edu!wilkerReferences:
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!noose.ecn.purdue.edu!mentor.cc.purdue.edu!descartes.math.purdue.edu!wilker From: wilker@descartes.math.purdue.edu (Clarence Wilkerson) Newsgroups: sci.electronics Subject: Re: Refreshing DRAM Message-ID: <16325@mentor.cc.purdue.edu> Date: 8 Nov 90 21:22:17 GMT References: <5093@navy22.UUCP> <39251@ut-emx.uucp> Sender: news@mentor.cc.purdue.edu Reply-To: wilker@descartes.math.purdue.edu (Clarence Wilkerson) Lines: 4