🚀 go-pugleaf

I don't know if its cheap, but the 1989 _Signetics Linear Data Manual
Volume 1: Communications_ has a chip called the NE568, called a "150 Mhz
Phase locked loop."  One component of a PLL is, of course, a VCO.
It looks like you should be able to use the VCO alone if want, although
the output would probably need some work to get to a logic signal.

Anybody know if this chip is any good?

While we're talking PLL's, does anyone have any suggestions on chips or other
approaches to using a PLL as a frequency synthesizer to generate 50 and 25 Mhz
ECL clocks that are in phase with an incomming 25Mhz ECL clock?  We'd prefer
the clocks to stay pretty close to the rated values even when the input
clock goes away, although the system really doesn't have to function that
way, so I suppose a VCXO is in order.   We need to clock in the incomming
data from the interface cable at 25Mhz and run some control logic at 50Mhz.
All the incomming signals are differential ECL, but we're planning to convert
to TTL right away, with the possible exception of the clock generation/
distribution stuff.     Thanks for any suggestions.

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Steve Tell      e-mail: tell@wsmail.cs.unc.edu usmail:  #5L Estes Park apts
CS Grad Student, UNC Chapel Hill.    919 968 1792       Carrboro NC 27510