🚀 go-pugleaf

In article <1990Nov15.025217.2246@Oxford.COM> wos@oxford.COM (Olin Sibert) writes:
  >
  >If one is doing it out of SSI (does anyone *do* that any more?
  >

One camp of people certainly does use SSI: the FutureBus+ folks.  They
strongly advocate the use of SSI bus interface chips which contain
four FutureBus transceivers. (using the "BTL" small-swing interface spec).
FutureBus+ plans to implement 128- and 256-bit wide busses using these
4-bit SSI chips, which are available from Signetics.  Some of the reasons
they give in favor of SSI are:

   1.  The small chips fit comfortably in a 24-pin leadless chip carrier
       which is a tiny package.  This means the parasitic elements introduced
       by the package (inductance on supplies, capacitance on bus signals)
       is drastically reduced, compared to a VLSI approach using one die
       in a large package with lots-o-pins.

   2.  The 24-pin package lets them use lavish numbers of power and ground
       terminals, so there is very little ground bounce --> more stable
       logic levels on the bus --> more reliable, faster.

   3.  People are a lot more likely to solder down a bunch of SSI 24-LCC's
       than they are to solder a big mama VLSI bus chip.  People just seem
       to feel better if a giant mother chip (costing big $$) is socketed.
       Thus the SSI implementation eliminates the parasitic inductance
       and capacitance of the socket.

   4.  It's easier to implement different widths of busses (vendor A has
       64b, vendor B has 128b, vendor Tektronix has 256b) from little
       "slices" in SSI than from great whacking VLSI's.  Especially
       useful in the case of control signals, arbitration lines, and
       other thingies on the bus that aren't data bits.

   5.  *IF* you want to, you can use higher current, power hungry bus
       transceiver circuits in an SSI design.  It's far easier to get 1/2
       watt out of each of 64 SSI chips than it is to get 32 watts out
       of one VLSI chip.  Note: FutureBus+ currently implements rather low
       power bus transceiver chips so this advantage is not exploited
       in present implementations.

   6.  The tiny 24-LCC packages can be plunked down on the printed circuit
       board right next to the backplane connector, RIGHT NEXT TO THE BUS
       PINS THEY HOOK UP TO.  So the printed circuit traces from the connector
       to the bus transceiver chip are absolutely as short as possible,
       which means teeny tiny "stubs" which means less reflections which
       means higher performance.  If on the other hand a single VLSI chip
       were used, the PCboard traces would have to "fan" away from the
       chip to all 128 or 256 bus pins on the connector, resulting in longer
       PCB traces and nastier stubs.

There are probably more arguments in favor; I've just forgotten them.

If you're really interested, two of the FutureBus honchos are on the net:
John Theus (johnt@opus.WV.TEK.COM)  and  Paul Borrill (borrill@sun.UUCP).

Regards,
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
	(408) 524-8308    mark@mips.com  {or ...!decwrl!mips!mark}