🚀 go-pugleaf

In <1990Nov18.225425.22234@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes:

>In article <2416@krafla.rhi.hi.is> adamd@rhi.hi.is (Adam David) writes:
>>I am interested in how RAM access times are specified. Say a 150ns RAM chip is
>>read and immediately written again without changing the address or deselecting
>>the chip between. What is the total time taken? The read cycle must take 150ns,
>>but when the write cycle begins the correct memory cell is already addressed.
>>How long does it take to actually write to (or read from) a memory cell without
>>considering addressing delays?

>It depends on the chip, is the fast answer.  Assuming you are talking about
>reading and then writing the *same* location -- you don't make that clear --
>then there can sometimes be a speed improvement.  A lot depends on the
>details of the memory technology you are using.

Yes, I definitely meant reading the memory contents before writing new data at
the same location. I was interested in the comparison between various types of
memory but am specifically interested in the newer pseudo-static DRAMs (with
on-chip refresh circuitry for times of little activity). I have no access to the
data sheets for any of these at present.

>You're also overlooking another complication:  the speed quoted for a chip
>is usually the read access time.  That is *not* necessarily the full time
>needed for a read cycle.  DRAMs, in particular, need recovery time after
>the read, and thus have a cycle time substantially longer than their access
>time.  On the other hand, they can also do read-modify-write cycles that
>take less time than independent reads and writes.  A DRAM data sheet will
>often spend five pages on functional description and electrical parameters,
>followed by ten pages of timing diagrams and tables of timing limits.  A
>precise answer would require a far more detailed question.

Let me guess... , pseudo-static DRAMs are still DRAMs although they have an
8-bit data path and non-multiplexed address lines. Therefore they have similar
characteristics internally and would take a while longer to complete a full
access cycle at any particular address than the quoted access times. With 150ns
RAM a single read cycle followed by a single write cycle would take 150ns plus
some recovery time, twice over. A combined read-write cycle would take twice
150ns plus the recovery time once. If this is true the write part of the cycle
may not begin until the first 150ns are over, to allow the data to be read.
Is this in fact the case? Does this then mean that no greater speed is possible
for data exchange operations without moving to faster components?

For completeness, here is the order of signals (still guessing):

                  ._______________________________________________.
Address lines. ___|  stable address of valid memory location      |_____
                  |_______________________________________________|

       _______________.                                       ._________
/CE.                  |_______________________________________|

       _________________.               ._______________________________
/OE.                    |_______________|
                                        
       ___________________________________.               ._____________
/WE.                                      |_______________|

                                      .__.._________________.
Data lines. __________________________|rd||stable write data|___________
                                      |__||_________________|


each horizontal bar represents 10 ns.

Is this the best performance we can expect from the memory chip?
Or must it be even worse for any/all single-ported devices?

Thanks for any replies.

Adam David.     adamd@rhi.hi.is