🚀 go-pugleaf

I am designing a multiprocessor and I have some questions about how to
design parts of it.

The backplane and the boards that will plug into it are special for
this machine, i.e., I'm not using VME, Futurebus, etc.  I need to know
how fast I can run the bus and what kind of drivers, connectors, and
termination that it will need.  Is modelling backplanes and bus
transceivers with a circuit simulator viable?  Each bus in this system
will have 8 boards on it, with between 16" and 40" of backplane trace
per signal wire.  I'd like to clock it at 40ns.  Is this possible?
Would I get a signal-quality benefit by using surface mounted drivers?
Arbitration can take several cycles, hold/ack can be pipelined, so I
don't need a round-trip time on the bus of 40ns.  Typical transfers on
the bus will be of 1024 cycles (lots of bulk data).  I don't mind using
non-ttl parts, but I can't use anything that makes it really
expensive.  We are trying to show how to build a general purpose
multiprocessor with hundreds of 20 MIPS processors without
paying a fortune for interconnect.

Pointers to books and articles on this subject are welcome.

Are there special low-capacitance PC boards or connectors that would
reduce cross-talk?  Are there any PC boards that have high power-plane
capacitance for a sort of built-in bypass?

Can anyone recommend PCB layout tools hosted on SUN/4's?  We have
Racal/Redac for the PC, but SUN/4's are so much nicer to use.  I've
also heard that Tango PCB is good, but I don't know if that runs on
SUN/4's.

Can anyone recommend a high performance DRAM controller for 60ns 4 Mbit
parts (it would be connected to Motorola 88000 CMMUs).  How about a
DRAM controller for 1 Mbit VRAMs?  (This system uses the serial side of
VRAMs for very high node-to-node bulk memory transfers.)

Thanks for any help that you can lend,

	Robert Bedichek             robertb@cs.washington.edu