🚀 go-pugleaf

> As a hobbyist electronician I have come across a real problem.
> For a certain project, I would need an oscillator with digital,
> LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range,
> 1 kHz to 100 MHz. Is this at all possible?

Your "HUGE" range is probably not a big problem.  You could probably use
fairly standard PLL synthesis techniques.  You might want to consider
running an oscillator at, say 200-300 MHz and mixing it with 200 MHz to
obtain 0-100 MHz.  This way you get to use a VCO which covers a small range
(1.5:1) which is not difficult.

The incredibly precise logarithmic control may be a real pain - just
consider the problem of accurately measuring 1 (log) bit in 32 bits with a
frequency counter - you might need an expensive counter with a very long
capture time to resolve 1KHz from 1KHz + 1 bit.  You didn't mention how fast
this thing is required to change frequency.

> Then the next problem would be just to divide this signal into eight
> lines, so that the lines would pulse (change state, whichever would be
> the easiest) alternately, in order. I mean: Line 1,then line 2, then line 3,
> and at each input pulse from the oscillator the next line would be activated.

A fast shift register might do the trick - or (gasp!) a state machine.

> This oscillator-divider pair would be used to control 8 memories, whose
> signals would be each in turn given to a D/A converter. 

It sounds like you might get more help if you described what your design
is supposed to do at a high level rather than a low level.  It sounds like
perhaps what you're doing could be solved other ways and maybe has been
done before.

			-Paul "Spice is the Variety of Life"
			bame@hpfcbig.sde.hp.com	N0KCL