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Article #9309Re: DRAM INTERFACE CONTROLLER
From: Joseph I. Chiu
Date: Sat, 05 Jan 1991 01:27
Date: Sat, 05 Jan 1991 01:27
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josephc@nntp-server.caltech.edu (Joseph I. Chiu) writes: >By the way, what you're probably looking at is latching A0-A11 on the memory's >A0-A11, and A11-A14 plus M0-M6 on the memory's A0-A11 (for RAS and CAS, >respectively). What you're doing is you're "latching" the first 12 bits >of your address to select the "row" and then the last 12 bits of the address >to select the "column" of the bit(s) you're interested in. Oooops, sorry - just realized a mistake... Exchange row and RAS with column and CAS (and vice-versa). The memory is more efficient with RAS having the higher order address bits... Sorry about that. -Joseph -- -- josephc@coil.caltech.edu ...Just another lost soul in the universe
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Path: arc1-ca.pugleaf.net!utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!usc!jarthur!nntp-server.caltech.edu!josephc From: josephc@nntp-server.caltech.edu (Joseph I. Chiu) Newsgroups: sci.electronics Subject: Re: DRAM INTERFACE CONTROLLER Message-ID: <1991Jan5.012724.11762@nntp-server.caltech.edu> Date: 5 Jan 91 01:27:24 GMT References: <steveh.662964261@tasman> <1991Jan5.010211.11543@nntp-server.caltech.edu> Distribution: sci Organization: California Institute of Technology, Pasadena Lines: 21