🚀 go-pugleaf

In article <1991Jan16.161646.9446@athena.cs.uga.edu> mcovingt@athena.cs.uga.edu (Michael A. Covington) writes:
>   In article <1991Jan14.205104.2829526@locus.com> dana@locus.com (Dana H. Myers) writes:
>   >
>   >Since we are assuming the power is disspated in capacitance, we'll
>   >use the simple form of capacitive reactance:
>   >...etc...
>
>       Er... Power is not dissipated in capacitance.  No such thing.
>       Only resistance can dissipate power.
>
>   Here's how CMOS dissipation works.
>
>   A CMOS chip dissipates power resistively while transitioning from one
>   state to the other, and while charging the input capacitance of another
>   chip. (That's how capacitance got into it... the capacitance does not
>   dissipate power, but it provides current flow through a resistance.)

Well, after reading several of these postings, I've noticed 2 things: the
thread following the mathematical derivation came to the correct conclusion,
that P=C*V^2*f.  Second, the the simpler explanations, while not strictly
wrong, are kind of missing the mark.

Mike's comment is half right: *STATIC* power is not dissipated thru
capacitance, only through resistance.  But *DYNAMIC* power is.  CMOS circuits
will dissipate some static power, but every little.  What is the mechanism for
this?  Look at a CMOS inverter (for those of you unfamiliar with CMOS, I'm
going to cheat and describe this in terms of switches instead of MOS
transistors):

		Vdd
		 |
        IN=0 -> /
		 |  Cload(OUTPUT)
		 +----||----+----->
		 |          |
	IN=1 -> /           |
		 |          |
		Vss        Vss

When the input is 1, the lower switch closes, pulling the output low and
discharging Cload.  When the input is 0, the upper switch closes and pulls the
output high, charging Cload.  Static power can only be dissipated when both
switches are closed, and that power will be Pstatic=IV=V^2/R, where
V=(Vdd-Vss), and I=V/R, where V is as above and R is the combined resistance of
both switches (which are really transistors).  But in the ideal case, this
never happens, so that static power dissipated in a CMOS circuit (I mean *FULL*
CMOS; there are circuits that are built in CMOS that don't strictly follow the
"Complimentary" rule of CMOS, but I'm ignoring these...) is zero.  In the real
case, the static power depends on the shape of the input signal.  If it's a
perfect square wave, then Pstatic = 0.  Since it will always be somewhat
non-square, there will be a short period of time when the input will be between
Vss and Vdd, and during that short period both switches are on (or at least
"partially on", since they are really transistors :-) and Pstatic > 0.  In
fact, one could say that Pstatic=(V^2*g)/R (roughly), where g is the percentage
of time during which the input signal is transitioning between Vss and Vdd, a
decidely small number in most cases.

So normally in CMOS, Pstatic << Pdymanic, which is why P=C*V^2*f doesn't have a
resistive portion (as Mike notes).  As Mike says, the C is the input load of a
following circuit (Cload here).  When the input to this inverter is toggled,
Cload is repeatedly charged and discharged (think of it as a "current pump",
(which it is in a sense :-)).  So current is being driven from Vdd to Vss, but
not statically, only dynamically (meaning only as the input to the inverter
changes).  Without going into the mathematics of it (as was already done quite
clearly), it is obvious that the amount of charge that can be moved is
proportional to frequency (f) of the input changing, as well as to the the size
of the the capacitive load (the "charge bucket").

Hope this explanation helps to explain why CMOS is typically a low-power logic
technology, and why the power dissipation (they really mean "dynamic" or "AC"
dissipation when they say this) goes up when the frequency does.
--
Disclaimer: All spelling and/or grammar in this document are guaranteed to be
            correct; any exseptions is the is wurk uv intter-net deemuns,.

Mike McManus                        Mike.McManus@FtCollins.NCR.COM, or
NCR Microelectronics                ncr-mpd!mikemc@ncr-sd.sandiego.ncr.com, or
2001 Danfield Ct.                   uunet!ncrlnk!ncr-mpd!garage!mikemc
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