🚀 go-pugleaf

A few days ago I asked if anyone could clarify a question I had with
the documentation for the M68HC11, and said I would post a summary for
others who may be interested.

Thanks for the replies.  My first problem was whether the external bus
is driven when the processor is reset in special bootstrap mode, my
confusion being caused because the IRV bit is initially set in the
HPRIO register.

Rand Gray <rand@zeta.sps.mot.com> of Motorola MCU Development Systems
was kind enough to clarify:

   IRV is active in SPECIAL TEST mode only, which is not what you are
   booting with.  You correctly surmise that there will be no
   contention.

Secondly, I wondered about whether I needed to terminate the CMOS
tri-state data bus, about which Rand continues:

   Unterminated inputs and inputs which are tri-stated should definitely
   be pulled up.  If you use a CMOS or HCMOS static RAM, you could easily
   get away with 470k pullups, as the typical leakage of the inputs is
   much less than the 1 microamp max leakage specified in the HC11 spec.

   A 10-pin SIP resistor network with common-bus circuit has pin 1 as
   common, and 2 through 10 available as pullups (or pulldowns).

Thanks for the help.  I am pleased to say that after a few evenings
with a soldering iron the processor seems to be working nicely.  I
plan to use it as the heart of a clock to pick up the standard time
and frequency transmission from Rugby, here in England.  Hence my wish
to keep power consumption to a minimum so I can run it using a
battery.

Thanks again,

Melvin Anderson      <ma@stl.stc.co.uk>

STC Technology Ltd., London Road, Harlow, Essex, England.