Article View: sci.electronics
Article #8180Re: Design a bar graph
From: Phillip M. Vogel
Date: Tue, 06 Nov 1990 01:31
Date: Tue, 06 Nov 1990 01:31
47 lines
2638 bytes
2638 bytes
In article <16307@s.ms.uky.edu> you threw down the gauntlet:
>I have three binary lines, for eight possible states (yeah, oh wow). How
>can one light seven LED's from this, with zero having all LED's off and
>seven lighting all seven of them, in bar graph fashion? A dot display is
>easy, but bar is tougher. As a final touch, one should tax each digital
>line with but one standard TTL load.
>
>I can think of two ways to implement this, but they both seem like too many
>parts have to be used. I wonder if anyone has a brainstorm out there. It's
>a bit surprising how tough this problem was (at least to me).
>
Ok, either use a ROM, PROM, PAL, PEEL, FPGA, FPLA,
Microproccessor, or whatever. But seriously, folks, this aint so
hard.
Use something like an NE590 (Signetics 3 to 8 demux), which is
something like a 74138 with high current high voltage open
collector outputs. Put all the LEDs in series with a ~20 mA
current source driving one end (the anode), and the cathodes
tied to each output of the 590. The only catch is that your
current source has to be able to put out a voltage of about 15 or
so volts, depending on the LEDs you use.
BTW, I didn't look up the specs on the 590, so I suppose it's
possible that the inputs represent more than one load. if so, the
you gotta use input buffers.
( these ->|- things are supposed to be LEDs )
____
20 mA>>> ____|-->|->|->|->|->|->|->|-
| | | | | | |
| | | | | | |
+---+--+--+--+--+--+--+--+
| Q1 Q2 Q3 Q4 Q5 Q6 Q7 |
| |
| I0 I1 I2 |
+--+-----+-----+---------+
| | |
Hey. if it don't work, well, it's worth what you paid for it; and
if it DOES work, well, gimme a dollar (hi Chris!).
Another FREE design from....
--
Phillip M. Vogel, President | #include <standard_disclaimer.h>
Bartal Design Group, Inc. Englewood, NJ | (201)567-1343 FAX:(201)568-2891
UUCP: pyrnj!bartal!phillip | Domain: phillip@bartal.crlabs.com
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arc1-ca.pugleaf.net!utzoo!attcan!uunet!fernwood!apple!sun-barr!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!ub!rutgers!pyrnj!bartal!phillipReferences:
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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!fernwood!apple!sun-barr!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!ub!rutgers!pyrnj!bartal!phillip From: phillip@bartal.CRLABS.COM (Phillip M. Vogel) Newsgroups: sci.electronics Subject: Re: Design a bar graph Message-ID: <423@bartal.CRLABS.COM> Date: 6 Nov 90 01:31:48 GMT References: <16307@s.ms.uky.edu> Sender: phillip@bartal.CRLABS.COM Reply-To: phillip@bartal.CRLABS.COM (Phillip M. Vogel) Organization: Bartal Design Group, Inc. Lines: 47