🚀 go-pugleaf

 
 
 
Wow.  I've been overwhelmed with replies, suggestions, tips, etc.  Many
thanks to everybody that took the time to E-mail me.
 
I'm pretty much convinced that the main problem is that although I solved
the problem of leaving the WE line floating by using a pull up resistor,
the uP is tugging the WE low as it dies.
 
Many people recommended I purchase one of the RAM-in-a-socket contraptions.
I'd prefer not to do it this way since this project is a hacking experience
for me.   I think I'm going to go with one of the power monitor chips that
will disable the RAM's CS as soon as it sees the main power start to fall.
 
Yet another question, aimed at David C: if the power monitor chip pro-
tects the RAM by putting in in low power mode (disabling one of the CS lines),
will this solve the problem of the rest of the circuit getting power through
the data lines?  I assume this can only happen through output lines and not
input lines.  
 
If the CS is just yanked inactive, then it really shouldn't matter what
the processor is doing.  The processor can do any number of things as
the power drops anyway.  Things on the processor end are basically 
unpredictable, so the RAM has to be protected directly.  Seems that the
NMI, RESET, and HALT related solutions wouldn't work.
 
 
Thanks again, everybody... lets keep this conversation going!  Interesting
stuff.
 
 
 
 
 
(By the way, DavidC, could you send the CRC code you mentioned?  )
(and, to the guy who E-Mailed me from Arizona or New Mex about   )
(robotics... I lost your address and my reply bounced.  Try again)


    Greg Bell_________________________________________________________
      Hardware hacker          |
      Electronics hobbyist     | UUCP:  uunet!serene!pnet12!gbell
      EE major at UC San Diego |