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UC BERKELEY EXTENSION PRESENTS 
3 SHORT COURSES

1) Multilevel Metallization for High-Performance Submicron
Circuits

2) Polycrystalline Silicon: Technology & Applications

3) Gate Oxide Damage from Plasma Processing


MULTILEVEL METALLIZATION FOR HIGH-
PERFORMANCE SUBMICRON CIRCUITS
April 26-28, 1995, San Francisco Airport

The first part of this course deals with the materials that are
widely used for submicron multilevel metallization. The main
interconnect material is still aluminum. The impact of
deposition equipment and conditions on the material properties
of Al film are discussed in the context of step coverage and
reliability of interconnects. How aluminum will be used all the
way down to submicron linewidths by the use of barrier metals
is also examined. Finally, solutions to problems encountered
with Al-based interconnects in multilevel metallization are
discussed.

Lecturers:

ROBERT S. BLEWER: Manager of the Advanced Silicon
Programs Dep't. in the Microelectronics and Photoconics
Directorate, and Director of the Contamination-Free
Manufacturing Research Center, Sandia National Laboratories,
Albuquerque, New Mexico.

NATHAN CHEUNG: Professor of Electrical Engineering &
Computer Sciences, University of California, Berkeley, and
Associate Faculty of Lawrence Berkeley Laboratory.

CALVIN T. GABRIEL: Principal Engineer in the Technology
Development Group at VLSI Technology, Inc., San Jose,
California.

DIPANKAR PRAMANIK (course organizer): Manager of
Process Development, VLSI Technology, Inc., San Jose,
California.


POLYCRYSTALLINE SILICON: TECHNOLOGY AND
APPLICATIONS
May 8-9, 1995, San Francisco Airport

This course emphasizes trends and models and uses specific
experimental data to illustrate these models. By understanding
the interrelation between deposition conditions and film
properties, optimum polysilicon layers can be designed for
specific applications. One microstructure no longer fits all
applications. The course is aimed at providing a framework
that allows the rapid and efficient experiments needed for
practical device fabrication.

Lecturers:

JOHN OGAWA BORLAND: Director of Process
Development, Ion Technology Division, Genus, Inc.,
Newburyport, Massachusetts.

TED KAMINS (course organizer): Project Leader at Hewlett-
Packard, Palo Alto, California, focusing on advanced CVD and
polysilicon topics.


GATE OXIDE DAMAGE FROM PLASMA PROCESSING
June 12-13, 1995, San Francisco Airport

This course provides an overview of what has been learned
recently about how plasma processing can damage thin oxides,
and to provide a framework for understanding this damage by
describing possible mechanisms. Test structures and techniques
will be described for measuring damage, enabling the
participant to design and carry out appropriate damage studies.
Strategies will be given for characterizing and minimizing
damage through plasma process equipment selection, hardware
modification, and process development. Finally, the role of
device design in damage will be examined.

Lecturers:

CALVIN T. GABRIEL: Principal Engineer in the Technology
Development Group at VLSI Technology, Inc., San Jose,
California.

CHENMING HU: Professor of Electrical Engineering &
Computer Sciences, University of California, Berkeley.

JAMES McVITTIE: Senior Research Scientist at the Stanford
University Center for Integrated Systems.


FOR FURTHER INFORMATION:

Please call or send us your mailing address

Continuing Education in Engineering
University of California, Berkeley Extension
2223 Fulton Street
Berkeley, CA 94720-7010

phone: 510-642-4151
fax: 510-643-8683