🚀 go-pugleaf

             Electrical Engineering Computer Group
                     Cider Seminar Series

                             BNR:
            How I Spent My (2 year) Summer Vacation

                              by
                         Mike Takefman
             Electrical Engineering Computer Group
                     University of Toronto

   Time: Friday, February 24, 1989, 12:05 --- Place: GB 220

       The  DMS-100  Application   is   fairly   resistant   to
  conventional  methods of speedup. The author spent almost two
  years with  the  Processor  Exploratory  group  designing  an
  architecture  that  would  provide a 2.5 times speedup by the
  early 1990's and would scale to a  5  times  speedup  by  the
  middle 1990's.

       The talk will consist of a short overview of research at
  BNR  followed  by  a discussion of the challenges involved in
  speeding    up    the    Call     Processing     Application.

                           Coming Soon

  Date          Who                        Topic

 March 6   Miriam Lesser   A Formal Approach to the Synthesis of
                           Combinational CMOS Circuits


-- 
  Duncan Elliott, Dept. EE, University of Toronto, Toronto, Canada M5S 1A5
  dunc@eecg.toronto.edu  dunc@eecg.utoronto.ca  uunet!utai!eecg!dunc
  LAT: 43 39' 35.9"N  LON: 79 23' 41.7"W ELEVATION: 349.30          VE3PKD